PEEL16CV8P-15 datasheet, PDF - EEWORLD Datasheet

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PEEL16CV8P-15: DescriptionEE PLD, 15ns, CMOS, PDIP20, 0.300 INCH, PLASTIC, DIP-20; CategoryProgrammable logic devices Programmable logic; File Size630KB，10 Pages; ManufacturerIntegrated Circuit Systems（IDT ）

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PEEL16CV8P-15 Overview

EE PLD, 15ns, CMOS, PDIP20, 0.300 INCH, PLASTIC, DIP-20

PEEL16CV8P-15 Parametric

Parameter Name	Attribute value
Maker	Integrated Circuit Systems（IDT ）
Parts packaging code	DIP
package instruction	DIP,
Contacts	20
Reach Compliance Code	unknown
maximum clock frequency	41.6 MHz
JESD-30 code	R-PDIP-T20
length	26.162 mm
Dedicated input times	9
Number of I/O lines	8
Number of terminals	20
Maximum operating temperature	70 °C
Minimum operating temperature
organize	9 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Programmable logic type	EE PLD
propagation delay	15 ns
Certification status	Not Qualified
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	7.62 mm
Base Number Matches	1

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PEEL16CV8P-15 Related Products

	PEEL16CV8P-15	PEEL16CV8J-15	PEEL16CV8S-15	PEEL16CV8T-15
Description	EE PLD, 15ns, CMOS, PDIP20, 0.300 INCH, PLASTIC, DIP-20	EE PLD, 15ns, CMOS, PQCC20, PLASTIC, LCC-20	EE PLD, 15ns, CMOS, PDSO20, SOIC-20	EE PLD, 15ns, CMOS, PDSO20, TSSOP-20
Maker	Integrated Circuit Systems（IDT ）	Integrated Circuit Systems（IDT ）	Integrated Circuit Systems（IDT ）	Integrated Circuit Systems（IDT ）
Parts packaging code	DIP	QLCC	SOIC	TSSOP
package instruction	DIP,	QCCJ,	SOP,	TSSOP,
Contacts	20	20	20	20
Reach Compliance Code	unknown	unknown	unknown	unknown
maximum clock frequency	41.6 MHz	41.6 MHz	41.6 MHz	41.6 MHz
JESD-30 code	R-PDIP-T20	S-PQCC-J20	R-PDSO-G20	R-PDSO-G20
length	26.162 mm	8.9662 mm	12.8 mm	6.5 mm
Dedicated input times	9	9	9	9
Number of I/O lines	8	8	8	8
Number of terminals	20	20	20	20
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C
organize	9 DEDICATED INPUTS, 8 I/O	9 DEDICATED INPUTS, 8 I/O	9 DEDICATED INPUTS, 8 I/O	9 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DIP	QCCJ	SOP	TSSOP
Package shape	RECTANGULAR	SQUARE	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	CHIP CARRIER	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Programmable logic type	EE PLD	EE PLD	EE PLD	EE PLD
propagation delay	15 ns	15 ns	15 ns	15 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum supply voltage	5.25 V	5.25 V	5.25 V	5.25 V
Minimum supply voltage	4.75 V	4.75 V	4.75 V	4.75 V
Nominal supply voltage	5 V	5 V	5 V	5 V
surface mount	NO	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	THROUGH-HOLE	J BEND	GULL WING	GULL WING
Terminal pitch	2.54 mm	1.27 mm	1.27 mm	0.65 mm
Terminal location	DUAL	QUAD	DUAL	DUAL
width	7.62 mm	8.9662 mm	7.5 mm	4.4 mm
Maximum seat height	-	4.369 mm	2.65 mm	1.2 mm

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