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M1020-12-161.1328LF

Description
Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36
CategoryWireless rf/communication    Telecom circuit   
File Size311KB,10 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
Download Datasheet Parametric View All

M1020-12-161.1328LF Overview

Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36

M1020-12-161.1328LF Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Parts packaging codeLCC
package instructionQCCN,
Contacts36
Reach Compliance Codecompli
JESD-30 codeS-CQCC-N36
JESD-609 codee3
length8.99 mm
Number of functions1
Number of terminals36
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeQCCN
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height3.1 mm
Nominal supply voltage3.3 V
surface mountYES
Telecom integrated circuit typesATM/SONET/SDH SUPPORT CIRCUIT
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formNO LEAD
Terminal pitch0.635 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width8.99 mm
Base Number Matches1
Integrated
Circuit
Systems, Inc.
Product Data Sheet
M1020/21
VCSO B
ASED
C
LOCK
PLL
G
ENERAL
D
ESCRIPTION
The M1020/21 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting up to 2.5Gb data rates.
It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M1020/21 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
MR_SEL3
GND
NC
DIF_REF0
nDIF_REF0
REF_SEL
DIF_REF1
nDIF_REF1
VCC
MR_SEL2
MR_SEL0
MR_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
27
26
25
24
23
22
21
20
19
28
29
30
31
32
33
34
35
36
M1020
M1021
(Top View)
18
17
16
15
14
13
12
11
10
P_SEL0
P_SEL1
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
F
EATURES
Integrated SAW delay line; low phase jitter of < 0.5ps
rms, typical (12kHz to 20MHz)
Output frequencies of 62.5 to 175 MHz
(Specify VCSO output frequency at time of order)
LVPECL clock output (CML and LVDS options available)
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
Loss of Lock (LOL) output pin
Narrow Bandwidth control input (NBW pin)
Hitless Switching (HS) options with or without Phase
Build-out (PBO) to enable SONET (GR-253) / SDH
(G.813) MTIE and TDEV compliance during reselection
Pin-selectable feedback and reference divider ratios
Industrial temperature grade available
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using
M1020-11-155.5200 or M1021-11-155.5200
Input Reference
Clock (MHz)
(M1020)
(M1021)
GND
GND
GND
OP_IN
nOP_OUT
nVC
VC
OP_OUT
nOP_IN
1
2
3
4
5
6
7
8
9
PLL Ratio
(Pin Selectable)
(M1020)
(M1021)
Output Clock
(MHz)
(Pin Selectable)
19.44 or 38.88
77.76
155.52
622.08
8 or 4
2
1
0.25
155.52
or
77.76
Table 1: Example I/O Clock Frequency Combinations
S
IMPLIFIED
B
LOCK
D
IAGRAM
Loop
Filter
M1020/21
NBW
LOL
MUX
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_SEL
MR_SEL3:0
4
Phase
Detector
0
1
R Div
VCSO
M Divider
M/R Divider
LUT
P Divider
(1, 2, or TriState)
TriState
FOUT0
nFOUT0
FOUT1
nFOUT1
P_SEL1:0
2
P Divider
LUT
Figure 2: Simplified Block Diagram
M1020/21 Datasheet Rev 1.0
M1020/21 VCSO Based Clock PLL
Revised 28Jul2004
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