DATA SHEET
µ
PC8130TA,
µ
PC8131TA
–15 dBm INPUT, VARIABLE GAIN AMPLIFIER SILICON MMIC
FOR TRANSMITTER AGC OF DIGITAL CELLULAR TELEPHONE
BIPOLAR ANALOG INTEGRATED CIRCUITS
DESCRIPTION
The
µ
PC8130TA and
µ
PC8131TA are silicon monolithic integrated circuits designed as variable gain amplifier.
Due to 800 MHz to 1.5 GHz operation, these ICs are suitable for RF transmitter AGC stage of digital cellular
telephone. These ICs are lower distortion than conventional
µ
PC8119T and
µ
PC8120T so that –15 dBm input level
can be applied. These ICs also available in two types of gain control so you can choose either IC in accordance with
your system design. 3 V supply voltage and minimold package contribute to make your system lower voltage,
decreased space and fewer components.
The
µ
PC8130TA and
µ
PC8131TA are manufactured using NEC’s 20 GHz f
T
NESAT™III silicon bipolar process.
This process uses silicon nitride passivation film and gold electrodes. These materials can protect chip surface from
external pollution and prevent corrosion/migration. Thus, this IC has excellent performance, uniformity and reliability.
FEATURES
• Recommended operating frequency: f = 800 MHz to 1.5 GHz
• Low distortion
: P
adj
≤
–60 dBc MAX. @P
in
= –15 dBm,
∆
f =
±50
kHz, V
CC
= 3.0 V,
T
A
= +25 °C
• Supply voltage
: V
CC
= 2.7 to 3.3 V
• Low current consumption
: I
CC
= 11 mA TYP. @V
CC
= 3.0 V
• Gain control voltage
: V
AGC
= 0 to 2.4 V (recommended)
• Two types of gain control
:
µ
PC8130TA = V
AGC
up vs. Gain up (Reverse control)
µ
PC8131TA = V
AGC
up vs. Gain down (Forward control)
• AGC control can be constructed by external control circuit.
• High-density surface mounting
: 6 pin minimold package
APPLICATION
• 800 MHz to 900 MHz or 1.5 GHz Digital cellular telephone (PDC800M, PDC1.5G and so on)
ORDERING INFORMATION
Part Number
Package
6-pin minimold
C2R
Marking
C2Q
Supplying Form
Embossed tape 8 mm wide.
1, 2, 3 pins face to perforation side of the tape.
Qty 3 kp/reel.
Gain Control Type
Reverse control
Forward control
µ
PC8130TA-E3
µ
PC8131TA-E3
Remark
To order evaluation samples, please contact your local NEC sales office.
(Part number for sample order:
µ
PC8130TA,
µ
PC8131TA)
Caution Electro-static sensitive devices.
The information in this document is subject to change without notice.
Document No. P11721EJ2V0DS00 (2nd edition)
Date Published October 1998 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1997
µ
PC8130TA,
µ
PC8131TA
PIN CONNECTIONS
(Top View)
(Bottom View)
4
4
3
Pin No.
1
2
Pin Name
INPUT
GND
GND
OUTPUT
V
CC
V
AGC
3
C2Q
2
5
5
2
3
4
1
6
6
1
5
6
Marking is an example of
µ
PC8130TA
GAIN CONTROL AMPLIFIER PRODUCT LINE-UP
Part No.
V
CC
(V)
4.5 to 5.5
2.7 to 3.3
2.7 to 3.3
2.7 to 3.3
2.7 to 3.3
I
CC
(mA)
15
11
11
11
11
V
AGC
(V)
3.3 to 5.0
0.6 to 2.4
0.6 to 2.4
0.6 to 2.4
0 to 2.4
V
AGC
up
vs.
Gain
down
down
up
up
down
f (GHz)
up to 1.1
0.1 to 1.92
0.1 to 1.92
0.8 to 1.5
0.8 to 1.5
P
O (1 dB)
–4
+3
+3
+5
+5
P
in
(dBm)
–
≤
–18
≤
–18
≤
–15
≤
–15
PHS, PDC
PHS, PDC
PDC 800 M, PDC 1.5 G
PDC 800 M, PDC 1.5 G
Features
µ
PC2723T
µ
PC8119T
µ
PC8120T
µ
PC8130TA
µ
PC8131TA
Remark
Typical performance. Please refer to ELECTRICAL CHARACTERISTICS in detail.
To know the associated product, please refer to each latest data sheet.
SYSTEM APPLICATION EXAMPLE
This block diagram is an example of IF modulation digital cellular system.
The
µ
PC8130TA and
µ
PC8131TA are applicable for not only IF modulation system but also RF modulation
system. This diagram is intended to show the
µ
PC8130TA and
µ
PC8131TA location in the systems.
RX
I
Q
DEMO
SW
÷N
PLL
PLL
µ
PC8130TA
or
µ
PC8131TA
TX
PA
I
0°
φ
90 °
Q
This document is to be specified for
µ
PC8130TA and
µ
PC8131TA only. For the other part number mentioned in
this document, please refer to the latest data sheet of each part number.
2
µ
PC8130TA,
µ
PC8131TA
PIN EXPLANATION
Applied
Voltage
V
–
Pin
Voltage
Note
V
1.4
Pin
No.
1
Pin
Name
IN
Function and Applications
Internal Equivalent Circuit
RF input pin. This pin should be
coupled with capacitor (eg 1000 pF)
for DC cut. Input return loss can be
improved with external impedance
matching circuit.
Ground pin. This pin should be
connected to system ground with
minimum inductance. Ground patt-
ern on the board should be formed
as wide as possible. Ground pins
must be connected together with
wide ground pattern to decrease
impedance difference.
RF output pin. This pin is designed
as open collector of high impedance.
This pin must be externally equipped
with matching circuits.
Control
circuit
5
4
2
3
GND
0
−
1
Bias
circuit
2
3
GND
4
OUT
voltage
as same
as V
CC
through
external
inductor
2.7 to 3.3
−
5
V
CC
–
Supply voltage pin.
This pin must be equipped with
bypass capacitor (eg 1000 pF)
to minimize its RF impedance.
Gain control pin. The relation
between product number and control
performance is shown below;
Part No.
V
AGC
up vs. Gain
up
down
2
6
5
6
V
AGC
0 to 3.3
−
Control circuit
µ
PC8130TA
µ
PC8131TA
Note
Pin voltage is measured at V
CC
= 3.0 V.
3
µ
PC8130TA,
µ
PC8131TA
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Total Circuit Current
Input Power
Gain Control Voltage
Operating Ambient Temperature
Storage Temperature
Symbol
V
CC
I
CC
P
in
V
AGC
T
A
T
stg
Conditions
T
A
= +25 °C, Pin 4 and 5
T
A
= +25 °C, Pin 4 and 5
T
A
= +25 °C
T
A
= +25 °C
Ratings
3.6
30
+10
3.6
–25 to +85
–55 to +150
Unit
V
mA
dBm
V
°C
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Symbol
V
CC
MIN.
2.7
TYP.
3.0
MAX.
3.3
Unit
V
Remarks
Same voltage should be applied to 4
and 5 pins.
–0.5
≤
I
AGC
≤
0.1 mA
P
adj
≤
–60 dBc @
∆
f =
±50
kHz
Note
Gain Control Voltage
Input Level
Operating Ambient Temperature
Operating Frequency
AGC Pin Drive Current
V
AGC
P
in
T
A
f
I
AGC
0
–
–25
800
0.5
–
–
+25
–
–
2.4
–15
+85
1500
–
V
dBm
°C
MHz
mA
With external output-matching
V
AGC
≤
3.3 V
Note
Adjacent Channel Interference (P
adj
) wave form condition:
π
/4DQPSK modulation signal, data rate = 42
kbps, rolloff ratio = 0.5, PN9 bits (pseudorandom pattern)
4
µ
PC8130TA,
µ
PC8131TA
ELECTRICAL CHARACTERISTICS (Unless otherwise specified, T
A
= +25 °C, V
CC
= V
out
= 3.0 V, Z
S
= Z
L
= 50
Ω
,
External matched output port)
µ
PC8130TA
MIN.
Circuit Current
Maximum Power
Gain
Gain Control
Note1
Range
Minimum Power
Gain
Adjacent Channel
Interference
Note 2
)
(@
∆
f =
±50
kHz
Isolation
I
CC
G
PMAX
No signal, I
CC
= I
Vcc
+ I
out
f = 950 MHz, P
in
= –20 dBm
f = 1440 MHz, P
in
= –20 dBm
f = 950 MHz, P
in
= –20 dBm
f = 1440 MHz, P
in
= –20 dBm
f = 950 MHz, P
in
= –20 dBm
f = 1440 MHz, P
in
= –20 dBm
f = 950 MHz, P
in
= –15 dBm
f = 1440 MHz, P
in
= –15 dBm
8.5
10
8
40
35
–
–
–
–
TYP.
11
12.5
11
50
41
–37
–30
–65
–65
MAX.
15
15
14
–
–
–
–
–60
–60
MIN.
8.5
9.5
8
40
35
–
–
–
–
Parameter
Symbol
Test Conditions
µ
PC8131TA
TYP.
11
12
11
45
39
–33
–28
–65
–65
MAX.
15
14.5
14
–
–
–
–
–60
–60
Unit
mA
dB
GCR
dB
G
PMIN
dB
P
adj
dB
ISL
f = 950 MHz, G
PMAX
f = 1440 MHz, G
PMAX
f = 950 MHz, G
PMAX
f = 1440 MHz, G
PMAX
f = 950 MHz, G
PMAX
f = 1440 MHz, G
PMAX
f = 950 MHz, G
PMAX
f = 1440 MHz, G
PMAX
17
20
+2
+2
3.5
6.5
–
–
20
25
+5
+5
6.5
10
11
8.5
–
–
–
–
–
–
14
11.5
20
25
+2
+1
6
7
–
–
25
30
+5
+4
9
10.5
11
8
–
–
–
–
–
–
14
11
dB
1 dB Compression
Output Power
Input Return
Loss
Noise Figure
P
O (1 dB)
dBm
RL
in
dB
NF
dB
Notes 1.
Gain Control Range (GCR) specification: GCR = G
PMAX
– G
PMIN
(dB)
Conditions
µ
PC8130TA: G
PMAX
@ V
AGC
= V
CC
, G
PMIN
@ V
AGC
= 0 V
µ
PC8131TA: G
PMAX
@ V
AGC
= 0 V, G
PMIN
@ V
AGC
= V
CC
2.
Adjacent Channel Interference (P
adj
) wave form condition:
π
/4DQPSK modulation signal, data rate = 42
kbps, rolloff ratio = 0.5, PN9 bits (pseudorandom pattern)
Remark
Measured on TEST CIRCUIT 1 and 2
5
Embedded System
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