DS34T104 datasheet, PDF - EEWORLD Datasheet

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DS34T104: DescriptionSingle/Dual/Quad/Octal TDM-over-Packet Chip; File Size1MB，16 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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Single/Dual/Quad/Octal TDM-over-Packet Chip

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ABRIDGED DATA SHEET

Rev: 101708

DS34T101, DS34T102, DS34T104, DS34T108

Single/Dual/Quad/Octal TDM-over-Packet Chip

General Description

These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC

compliant devices allow up to eight E1, T1 or serial

streams or one high-speed E3, T3, STS-1 or serial

stream to be transported transparently over IP, MPLS

or Ethernet networks. Jitter and wander of recovered

clocks conform to G.823/G.824, G.8261, and TDM

specifications. TDM data is transported in up to 64

individually configurable bundles. All standards-

based TDM-over-packet mapping methods are

supported except AAL2. Frame-based serial HDLC

data flows are also supported. With built-in full-

featured E1/T1 framers and LIUs. These ICs

encapsulate the TDM-over-packet solution from

analog E1/T1 signal to Ethernet MII while preserving

options to make use of TDM streams at key

intermediate points. The high level of integration

available with the DS34T10x devices minimizes cost,

board space, and time to market.

♦

Features

Full-Featured IC Includes E1/T1 LIUs and

Framers, TDMoP Engine, and 10/100 MAC

Transport of E1, T1, E3, T3 or STS-1 TDM or

CBR Serial Signals Over Packet Networks

Full Support for These Mapping Methods:

SAToP, CESoPSN, TDMoIP (AAL1), HDLC,

Unstructured, Structured, Structured with CAS

Adaptive Clock Recovery, Common Clock,

External Clock and Loopback Timing Modes

On-Chip TDM Clock Recovery Machines, One

Per Port, Independently Configurable

Clock Recovery Algorithm Handles Network

PDV, Packet Loss, Constant Delay Changes,

Frequency Changes and Other Impairments

64 Independent Bundles/Connections

Multiprotocol Encapsulation Supports IPv4,

IPv6, UDP, RTP, L2TPv3, MPLS, Metro Ethernet

VLAN Support According to 802.1p and 802.1Q

10/100 Ethernet MAC Supports MII/RMII/SSMII

Selectable 32-Bit, 16-Bit or SPI Processor Bus

Operates from Only Two Clock Signals, One for

Clock Recovery and One for Packet Processing

Glueless SDRAM Buffer Management

Low-Power 1.8V Core, 3.3V I/O

Applications

TDM Circuit Extension Over PSN

Leased-Line Services Over PSN

TDM Over GPON/EPON

TDM Over Cable

TDM Over Wireless

Cellular Backhaul Over PSN

Multiservice Over Unified PSN

HDLC-Based Traffic Transport Over PSN

See detailed feature list in Section

Functional Diagram

CPU

Bus

Ordering Information

PART

DS34T101GN

DS34T101GN+*

DS34T102GN

DS34T102GN+

DS34T104GN

DS34T104GN+

DS34T108GN

DS34T108GN+

PORTS TEMP RANGE

-40°C to +85°C

PIN-PACKAGE

484 TEBGA

484 HSBGA

DS34T108

Octal

E1/T1/J1

Transceiver

Framers

Circuit

Emulation

Engine

10/100

Ethernet

MAC

xMII

E1/T1

Interfaces

BERT

& CAS

LIUs

Manager

Buffer

Clock

Adapters

TDM

Access

SDRAM

Interface

Clock Inputs

+Denotes

lead-free/RoHS-compliant package (explanation).

Future product—contact factory for availability.

________________________________________________________

Maxim Integrated Products

Some revisions of this device may incorporate deviations from published specifications known as errata.

Multiple revisions of any device may be simultaneously available through various sales channels. For

information about device errata, go to:

www.maxim-ic.com/errata.

For pricing, delivery, and ordering

information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

ABRIDGED DATA SHEET

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108

SPECIFICATION

O.161

Y.1413

Y.1414

Y.1452

Y.1453

MEF

MEF 8

MFA

MFA 4.0

MFA 5.0.0

MFA 8.0.0

SPECIFICATION TITLE

In-Service Code Violation Monitors for Digital Systems

(1993)

TDM-MPLS Network Interworking – User Plane Interworking

(03/2004)

Voice Services–MPLS Network Interworking

(07/2004)

Voice Trunking over IP Networks

(03/2006)

TDM-IP Interworking – User Plane Networking

(03/2006)

Implementation Agreement for the Emulation of PDH Circuits over Metro Ethernet Networks

(10/2004)

TDM Transport over MPLS Using AAL1

(06/2003)

I.366.2 Voice Trunking Format over MPLS Implementation Agreement (08/2003)

Emulation of TDM Circuits over MPLS Using Raw Encapsulation – Implementation

Agreement

(11/2004)

2 Detailed Description

The DS34T108 is an 8-port device integrating a sophisticated multiport TDM-over-Packet (TDMoP) core and eight

full-featured, independent, software-configurable E1/T1 transceivers. The DS34T104, DS34T102 and DS34T101

have the same functionality as the DS34T108, except they have only 4, 2 or 1 ports and transceivers, respectively.

Each E1/T1 transceiver is composed of a line interface unit (LIU), a framer, an elastic store, an HDLC controller

and a bit error rate tester (BERT) block. These transceivers connect seamlessly to the TDMoP block to form a

complete solution for mapping and demapping E1/T1 to and from IP, MPLS or Ethernet networks. A MAC built into

the TDMoP block supports connectivity to a single 10/100 Mbps PHY over an MII, RMII or SSMII interface. The

DS34T10x devices are controlled through a 16 or 32-bit parallel bus interface or a high-speed SPI serial interface.

TDM-over-Packet Core

The TDM-over-Packet (TDMoP) core is the enabling block for circuit emulation and other network applications. It

performs transparent transport of legacy TDM traffic over Packet Switched-Networks (PSN). The TDMoP core

implements payload mapping methods such as AAL1 for circuit emulation, HDLC method, structure-agnostic

SAToP method, and the structure-aware CESoPSN method.

The AAL1 payload-type machine maps and demaps E1, T1, E3, T3, STS-1 and other serial data flows into and out

of IP, MPLS or Ethernet packets, according to the methods described in ITU-T Y.1413, Y.1453, MEF 8, MFA 4.1

and IETF RFC 5087 (TDMoIP). It supports E1/T1 structured mode with or without CAS, using a timeslot size of 8

bits, or unstructured mode (carrying serial interfaces, unframed E1/T1 or E3/T3/STS-1 traffic).

The HDLC payload-type machine maps and demaps HDLC dataflows into and out of IP/MPLS packets according

to IETF RFC 4618 (excluding clause 5.3 – PPP) and IETF RFC 5087 (TDMoIP). It supports 2-, 7- and 8-bit timeslot

resolution (i.e. 16, 56, and 64 kbps respectively), as well as N × 64 kbps bundles (n=1 to 32). Supported

applications of this machine include trunking of HDLC-based traffic (such as Frame Relay) implementing Dynamic

Bandwidth Allocation over IP/MPLS networks and HDLC-based signaling interpretation (such as ISDN D-channel

signaling termination – BRI or PRI, V5.1/2, or GR-303).

The SAToP payload-type machine maps and demaps unframed E1, T1, E3 or T3 data flows into and out of IP,

MPLS or Ethernet packets according to ITU-T Y.1413, Y.1453, MEF 8, MFA 8.0.0 and IETF RFC 4553. It supports

E1/T1/E3/T3 with no regard for the TDM structure. If TDM structure exists it is ignored, allowing this to be the

simplest mapping/demapping method. The size of the payload is programmable for different services. This

emulation suits applications where the provider edges have no need to interpret TDM data or to participate in the

TDM signaling. The PSN network must have almost no packet loss and very low packet delay variation (PDV) for

this method.

The CESoPSN payload-type machine maps and demaps structured E1, T1, E3 or T3 data flows into and out of IP,

MPLS or Ethernet packets with static assignment of timeslots inside a bundle according to ITU-T Y.1413, Y.1453,

Rev: 101708

3 of 16

ABRIDGED DATA SHEET

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108

MEF 8, MFA 8.0.0 and the IETF RFC 5086 (CESoPSN). It supports E1/T1/E3/T3 while taking into account the

TDM structure. The level of structure must be chosen for proper payload conversion such as the framing type (i.e.

frame or multiframe). This method is less sensitive to PSN impairments but lost packets could still cause service

interruption.

E1/T1 Transceivers

The LIU in each transceiver is composed of a transmitter, a receiver and a jitter attenuator. Internal software

configurable impedance matching is provided for both transmit and receive paths, reducing external component

count. The transmit interface is responsible for generating the necessary waveshapes for driving the E1/T1 twisted

pair or coax cable and providing the correct source impedance depending on the type of cable used. T1 waveform

generation includes DSX–1 line build-outs as well as CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB. E1

waveform generation includes G.703 waveshapes for both 75Ω coax and 120Ω twisted cables. The receive

interface provides the correct line termination and recovers clock and data from the incoming line. The receive

sensitivity adjusts automatically to the incoming signal level and can be programmed for 0dB to -43dB or 0dB to

-12dB for E1 applications and 0dB to -15dB or 0dB to -36dB for T1 applications. The jitter attenuator removes

phase jitter from the transmitted or received signal. The crystal-less jitter attenuator can be placed in either the

transmit or receive path and requires only a T1- or E1-rate reference clock, which is typically synthesized by the

CLAD1 block from a common reference frequency of 10MHz, 19.44MHz, 38.88MHz or 77.76MHz.

In the framer block, the transmit formatter takes data from the TDMoP core, inserts the appropriate framing

patterns and alarm information, calculates and inserts CRC codes, and provides the HDB3 or B8ZS encoding (zero

code suppression) and AMI line coding. The receive framer decodes AMI, HDB3 and B8ZS line coding, finds frame

and multiframe alignment in the incoming data stream, reports alarm information, counts framing/coding/CRC

errors, and provides clock, data, and frame-sync signals to the TDMoP core.

Both transmit and receive paths have built-in HDLC controller and BERT blocks. The HDLC blocks can be

assigned to any timeslot, a portion of a timeslot or to the FDL (T1) or Sa bits (E1). Each controller has 64-byte

FIFOs, reducing the amount of processor overhead required to manage the flow of data. The BERT blocks can

generate and synchronize with pseudo-random and repetitive patterns, insert errors (singly or at a constant error

rate) and detect and count errors to calculate bit error rates.

Rev: 101708

4 of 16

DS34T104 Related Products

	DS34T104	DS34T101	DS34T102	DS34T101_08
Description	Single/Dual/Quad/Octal TDM-over-Packet Chip	Single/Dual/Quad/Octal TDM-over-Packet Chip	Single/Dual/Quad/Octal TDM-over-Packet Chip	Single/Dual/Quad/Octal TDM-over-Packet Chip

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