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MM74C240 • MM74C244 Inverting • Non-Inverting Octal Buffer and Line Driver with 3-STATE Outputs
October 1987
Revised May 2002
MM74C240 • MM74C244
Inverting • Non-Inverting Octal Buffer and
Line Driver with 3-STATE Outputs
General Description
The MM74C240 and MM74C244 octal buffers and line
drivers are monolithic complementary MOS (CMOS) inte-
grated circuits with 3-STATE outputs. These outputs have
been specially designed to drive highly capacitive loads
such as bus-oriented systems. These devices have a fan
out of 6 low power Schottky loads. A high logic level on the
output disable control input G makes the outputs go into
the high impedance state.
Features
s
Wide supply voltage range (3V to 15V)
s
High noise immunity (0.45 V
CC
typ)
s
Low power consumption
s
High capacitive load drive capability
s
3-STATE outputs
s
Input protection
s
TTL compatibility
s
20-pin dual-in-line package
s
High speed 25 ns (typ.) @ 10V, 50 pF (MM74C244)
Ordering Code:
Order Number
MM74C240WM
MM74C240N
MM74C244WM
MM74C244N
Package Number
M20B
N20A
M20B
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagrams
MM74C240
MM74C244
(Top View)
(Top View)
© 2002 Fairchild Semiconductor Corporation
DS005905
www.fairchildsemi.com
MM74C240 • MM74C244
Logic Diagrams
MM74C240
MM74C244
Truth Tables
MM74C240
ODA
1
1
0
0
ODB
1
1
0
0
1
=
HIGH
0
=
LOW
MM74C244
OA
Z
Z
1
0
OB
Z
Z
1
0
X
=
Don’t Care
Z
=
3-STATE
IA
X
X
0
1
IB
X
X
0
1
ODA
1
1
0
0
ODB
1
1
0
0
IA
X
X
0
1
IB
X
X
0
1
OA
Z
Z
0
1
OB
Z
Z
0
1
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2
MM74C240 • MM74C244
Absolute Maximum Ratings
(Note 1)
Voltage at Any Pin
Operating Temperature Range
Storage Temperature Range
Power Dissipation
Dual-In-Line
Small Outline
Operating V
CC
Range
Absolute Maximum V
CC
Lead Temperature
(Soldering, 10 seconds)
260
°
C
700 mW
500 mW
3V to 15V
18V
Note 1:
“Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Range”
they are not meant to imply that the devices should be operated at these
limits. The Electrical Characteristics table provides conditions for actual
device operation.
−
0.3V to V
CC
+
0.3V
−
55
°
C to
+
125
°
C
−
65
°
C to
+
150
°
C
DC Electrical Characteristics
Min/Max limits apply across temperature range, unless otherwise noted
Symbol
Parameter
Conditions
CMOS TO CMOS
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
I
OZ
I
IN(1)
I
IN(0)
I
CC
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
I
SOURCE
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
3-STATE Output Current
Logical “1” Input Current
Logical “0” Input Current
Supply Current
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
Output Source Current
(P-Channel)
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V, I
O
= −10 µA
V
CC
=
10V, I
O
= −10 µA
V
CC
=
5V, I
O
=
10
µA
V
CC
=
10V, I
O
=
10
µA
V
CC
=
10V, OD
=
V
IH
V
CC
=
15V, V
IN
=
15V
V
CC
=
15V, V
IN
=
0V
V
CC
=
15V
V
CC
=
4.75V
V
CC
=
4.75V
V
CC
=
4.75V, I
O
= −450 µA
V
CC
=
4.75V, I
O
= −2.2
mA
V
CC
=
4.75V, I
O
=
2.2 mA
V
CC
=
5V, V
OUT
=
0V
T
A
=
25°C
V
CC
=
10V, V
OUT
=
0V
T
A
=
25°C
I
SINK
Output Sink Current
(N-Channel)
V
CC
=
5V, V
OUT
=
V
CC
T
A
=
25°C
V
CC
=
10V, V
OUT
=
V
CC
T
A
=
25°C
48
70
mA
12
20
mA
−36
−70
mA
−14
−30
OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current)
mA
V
CC
−
0.4
2.4
0.4
V
CC
−
1.5
0.8
−1.0
0.005
−0.005
0.05
300
4.5
9.0
0.5
1.0
±10
1.0
3.5
8.0
1.5
2.0
V
V
V
V
µA
µA
µA
µA
V
V
V
V
V
Min
Typ
Max
Units
CMOS/LPTTL INTERFACE
3
www.fairchildsemi.com
MM74C240 • MM74C244
AC Electrical Characteristics
T
A
=
25
°
C, C
L
=
50 pF, unless otherwise specified
Symbol
t
PD(1)
,
t
PD(0)
Parameter
Propagation Delay
(Data In to Out)
MM74C240
(Note 2)
Conditions
Min
Typ
Max
Units
V
CC
=
5V, C
L
=
50 pF
V
CC
=
10V, C
L
=
50 pF
V
CC
=
5V, C
L
=
150 pF
V
CC
=
10V, C
L
=
150 pF
60
40
80
60
45
25
60
40
45
35
50
30
45
30
75
50
90
70
110
90
70
50
90
70
80
60
90
60
80
60
140
100
ns
ns
ns
MM74C244
V
CC
=
5V, C
L
=
50 pF
V
CC
=
10V, C
L
=
50 pF
V
CC
=
5V, C
L
=
150 pF
V
CC
=
10V, C
L
=
150 pF
t
1H
, t
0H
Propagation Delay Output
Disable to High Impedance
State (from a Logic Level)
R
L
=
1k, C
L
=
50 pF
V
CC
=
5V
V
CC
=
10V
R
L
=
1k, C
L
=
50 pF
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V, C
L
=
50 pF
V
CC
=
10V, C
L
=
50 pF
V
CC
=
5V, C
L
=
150 pF
V
CC
=
10V, C
L
=
150 pF
ns
ns
t
H1
, t
H0
Propagation Delay Output
Disable to Logic Level
(from High Impedance State)
t
T(HL)
, t
T(LH)
Transition Time
C
PD
Power Dissipation
Capacitance
(Output Enabled per Buffer)
MM74C240
MM74C244
(Output Disabled per Buffer)
MM74C240
MM74C244
(Note 3)
100
100
10
0
V
IN
=
0V, f
=
1 MHz, T
A
=
25°C
V
IN
=
0V, f
=
1 MHz, T
A
=
25°C
10
10
pF
pF
pF
pF
C
IN
C
O
Input Capacitance (Note 4)
(Any Input)
Output Capacitance (Note 4)
(Output Disabled)
Note 2:
AC Parameters are guaranteed by DC correlated testing.
Note 3:
C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note,
AN-90.
Note 4:
Capacitance is guaranteed by periodic testing.
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