1. Features
•
One of a Family of Devices with User Memories from 1-Kbit to 8-Kbits
•
8-Kbit (1-Kbyte) EEPROM User Memory
– Eight 1-Kbit (128-byte) Zones
– Self-timed Write Cycle
– Single Byte or 16-byte Page Write Mode
– Programmable Access Rights for Each Zone
2-Kbit Configuration Zone
– 37-byte OTP Area for User-defined Codes
– 160-byte Area for User-defined Keys and Passwords
High Security Features
– 64-bit Mutual Authentication Protocol (Under License of ELVA)
– Cryptographic Message Authentication Codes (MAC)
– Stream Encryption
– Four Key Sets for Authentication and Encryption
– Eight Sets of Two 24-bit Passwords
– Anti-Tearing Function
– Voltage and Frequency Monitors
Smart Card Features
– ISO 7816 Class B (3V) Operation
– ISO 7816-3 Asynchronous T=0 Protocol (Gemplus® Patent)
– Multiple Zones, Key Sets and Passwords for Multi-application Use
– Synchronous 2-wire Serial Interface for Faster Device Initialization
– Programmable 8-byte Answer-To-Reset Register
– ISO 7816-2 Compliant Modules
Embedded Application Features
– Low Voltage Operation: 2.7V – 3.6V
– Secure Nonvolatile Storage for Sensitive System or User Information
– 2-wire Serial Interface
– 1.0 MHz Compatibility for Fast Operation
– Standard 8-lead Plastic Packages
– Same Pin Configuration as AT24CXXX Serial EEPROM in SOIC and PDIP Packages
High Reliability
– Endurance: 100,000 Cycles
– Data Retention: 10 years
– ESD Protection: 2,000V min
•
CryptoMemory
AT88SC0808CA
•
•
Summary
•
•
Table 1-1.
Pad
VCC
GND
SCL/CLK
SDA/IO
RST
Pads
Description
Supply Voltage
Ground
Serial Clock Input
Serial Data Input/Output
Reset Input
ISO Module
C1
C5
C3
C7
C2
“SOIC, PDIP”
8
4
6
5
NC
TSSOP
8
1
6
3
NC
5204AS–CRYPT–7/08
Smart Card Module
VCC=C1
RST=C2
SCL/CLK=C3
NC=C4
C5=GND
C6=NC
C7=SDA/IO
C8=NC
8-lead SOIC, PDIP
NC
NC
NC
GND
8-lead TSSOP
VCC
NC
SCL
1
2
3
4
8
7
6
5
NC
NC
SDA
1
2
3
4
8-Lead TSSOP
8
7
6
5
VCC
NC
SCL
NC
SDA
GND
2. Description
The AT88SC0808CA member of the CryptoMemory® family is a high-performance secure
memory providing 8 Kbit of user memory with advanced security and cryptographic features built
in. The user memory is divided into eight 128-byte zones, each of which may be individually set
with different security access rights or effectively combined together to provide space for 1 to 8
data files. The AT88SC0808CA features an enhanced command set that allows direct communi-
cation with microcontroller hardware 2-Wire interface thereby allowing for faster firmware
development with reduced code space requirements.
3. Smart Card Applications
The AT88SC0808CA provides high security, low cost, and ease of implementation without the
need for a microprocessor operating system. The embedded cryptographic engine provides for
dynamic, symmetric-mutual authentication between the device and host, as well as performing
stream encryption for all data and passwords exchanged between the device and host. Up to
four unique key sets may be used for these operations. The AT88SC0808CA offers the ability to
communicate with virtually any smart card reader using the asynchronous T = 0 protocol (Gem-
plus Patent) defined in ISO 7816-3.
4. Embedded Applications
Through dynamic, symmetric-mutual authentication, data encryption, and the use of crypto-
graphic Message Authentication Codes (MAC), the AT88SC0808CA provides a secure place for
storage of sensitive information within a system. With its tamper detection circuits, this informa-
tion remains safe even under attack. A 2-wire serial interface running at speeds up to 1.0 MHz
provides fast and efficient communications with up to 15 individually addressable devices. The
AT88SC0808CA is available in industry standard 8-lead packages with the same familiar pin
configuration as AT24CXXX serial EEPROM devices.
Note:
Does not apply to TSSOP Pinout.
2
AT88SC0808CA
5204AS–CRYPT–7/08
AT88SC0808CA
Figure 4-1.
Block Diagram
VCC
GND
Power
Management
Authentication,
Encryption and
Certification Unit
Random
Generator
Synchronous
Interface
SCL/CLK
SDA/IO
RST
Asynchronous
ISO Interface
Reset Block
Data Transfer
Password
Verification
Answer to Reset
EEPROM
5. Pin Descriptions
5.1
Supply Voltage (VCC)
The VCC input is a 2.7V to 3.6V positive voltage supplied by the host.
5.2
Clock (SCL/CLK)
When using the asynchronous T = 0 protocol, the CLK (SCL) input provides the device with a
carrier frequency f. The nominal length of one bit emitted on I/O is defined as an “elementary
time unit” (ETU) and is equal to 372/f.
When using the synchronous protocol, data clocking is done on the positive edge of the clock
when writing to the device and on the negative edge of the clock when reading from the device.
5.3
Reset (RST)
The AT88SC0808CA provides an ISO 7816-3 compliant asynchronous Answer-To-Reset (ATR)
sequence. Upon activation of the reset sequence, the device outputs bytes contained in the 64-
bit Answer-To-Reset register. An internal pull-up on the RST input pad allows the device to oper-
ate in synchronous mode without bonding RST. The AT88SC0808CA does not support an
Answer-To-Reset sequence in the synchronous mode of operation.
5.4
Serial Data (SDA/IO)
The SDA/IO pin is bidirectional for serial data transfer. This pin is open-drain driven and may be
wired with any number of other open-drain or open-collector devices. An external pull-up resistor
should be connected between SDA/IO and VCC. The value of this resistor and the system
capacitance loading the SDA/IO bus will determine the rise time of SDA/IO. This rise time will
determine the maximum frequency during read operations. Low value pull-up resistors will allow
higher frequency operations while drawing higher average power supply current. SDA/IO infor-
mation applies to both asynchronous and synchronous protocols.
3
5204AS–CRYPT–7/08
6. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the oper-
ational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of
time may affect device reliability.
Absolute Maximum Ratings
Operating Temperature ..................................... -40⋅C to +85⋅C
Storage Temperature
..........................................−65
⋅
C to +150⋅C
Voltage on Any Pin
with Respect to Ground
.................................... −0.7
to V
cc
+0.7V
Maximum Operating Voltage............................................. 6.0V
DC Output Current ........................................................ 5.0 mA
Table 6-1.
DC Characteristics
Applicable over recommended operating range from V
CC
= +2.7 to 3.6V,
T
AC
= -40⋅C to +85⋅C (unless otherwise noted)
Symbol
V
CC
I
CC
I
CC
I
CC
I
CC
I
SB
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
I
IL
I
IL
I
IL
I
IH
I
IH
I
IH
V
OH
V
OL
I
OH
I
OL
Parameter
Supply Voltage
Supply Current
Supply Current
Supply Current
Supply Current
Standby Current
SDA/IO Input Low Voltage
CLK Input Low Voltage
RST Input Low Voltage
SDA/IO Input High Voltage
SCL/CLK Input High Voltage
RST Input High Voltage
SDA/IO Input Low Current
SCL/CLK Input Low Current
RST Input Low Current
SDA/IO Input High Current
SCL/CLK Input High Current
RST Input High Current
SDA/IO Output High Voltage
SDA/IO Output Low Voltage
SDA/IO Output High Current
SDA/IO Output Low Current
0 < VIL < VCC x 0.15
0 < VIL < VCC x 0.15
0 < VIL < VCC x 0.15
VCC x 0.7 < VIH < VCC
VCC x 0.7 < VIH < VCC
VCC x 0.7 < VIH < VCC
20K ohm external pull-up
IOL = 1mA
VOH
VOL
VCC x 0.7
0
Async READ at 3.57MHz
Async WRITE at 3.57MHz
Synch READ at 1MHz
Synch WRITE at 1MHz
VIN = VCC or GND
0
0
0
VCC x 0.7
VCC x 0.7
VCC x 0.7
Test Condition
Min
2.7
Typ
Max
3.6
5
5
5
5
100
VCC x 0.2
VCC x 0.2
VCC x 0.2
VCC
VCC
VCC
15
15
50
20
100
150
VCC
VCC x 0.15
20
10
Units
V
mA
mA
mA
mA
uA
V
V
V
V
V
V
uA
uA
uA
uA
uA
uA
V
V
uA
mA
4
AT88SC0808CA
5204AS–CRYPT–7/08
AT88SC0808CA
Table 6-2.
AC Characteristics
Parameter
f
CLK
f
CLK
Async Clock Frequency
Synch Clock Frequency
Clock Duty cycle
t
R
t
F
t
R
t
F
t
AA
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
SU.STO
t
DH
t
WR
“Rise Time - SDA/IO, RST”
“Fall Time - SDA/IO, RST”
Rise Time - SCL/CLK
Fall Time - SCL/CLK
Clock Low to Data Out Valid
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
200
200
10
100
200
20
5
Min
1
0
40
Max
4
1
60
1
1
9% x period
9% x period
250
Units
MHz
MHz
%
uS
uS
uS
uS
nS
nS
nS
nS
nS
nS
nS
mS
Applicable over recommended operating range from V
CC
= +2.7 to 3.6V, T
AC
= -40°C to +85°C, CL = 30pF (unless otherwise noted)
7. Device Operations for Synchronous Protocols
7.1
Clock and Data Transitions
The SDA pin is normally pulled high with an external device. Data on the SDA pin may change
only during SCL low time periods (see
Figure 7-3 on page 6).
Data changes during SCL high
periods will indicate a start or stop condition as defined below.
7.1.1
Start Condition
A high-to-low transition of SDA with SCL high defines a START condition which must precede all
commands (see
Figure 7-4 on page 7).
Stop Condition
A low-to-high transition of SDA with SCL high defines a STOP condition. After a read sequence,
the STOP condition will place the EEPROM in a standby power mode (see
Figure 7-4 on page
7).
ACKNOWLEDGE
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero to acknowledge that it has received each word. This happens dur-
ing the ninth clock cycle (see
Figure 7-5 on page 7).
7.1.2
7.1.3
5
5204AS–CRYPT–7/08
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