Features
•
One of a Family of 9 Devices with User Memories from 1-Kbit to 256-Kbit
•
128-Kbit (16-Kbyte) EEPROM User Memory
– Sixteen 1-Kbyte (8-Kbit) Zones
– Self-timed Write Cycle
– Single Byte or 128-byte Page Write Mode
– Programmable Access Rights for Each Zone
2-Kbit Configuration Zone
– 37-byte OTP Area for User-defined Codes
– 160-byte Area for User-defined Keys and Passwords
High Security Features
– 64-bit Mutual Authentication Protocol (Under License of ELVA)
– Encrypted Checksum
– Stream Encryption
– Four Key Sets for Authentication and Encryption
– Eight Sets of Two 24-bit Passwords
– Anti-tearing Function
– Voltage and Frequency Monitor
Smart Card Features
– ISO 7816 Class A (5V) or Class B (3V) Operation
– ISO 7816-3 Asynchronous T = 0 Protocol (Gemplus
®
Patent)
– Supports Protocol and Parameters Selection for Faster Operation
– Multiple Zones, Key Sets and Passwords for Multi-application Use
– Synchronous 2-wire Serial Interface for Faster Device Initialization
– Programmable 8-byte Answer-to-reset Register
– ISO 7816-2 Compliant Modules
Embedded Application Features
– Low Voltage Operation: 2.7V to 5.5V
– Secure Nonvolatile Storage for Sensitive System or User Information
– 2-wire Serial Interface
– 1.0 MHz Compatibility for Fast Operation
– Standard 8-lead Plastic Packages
– Same Pinout as 2-wire Serial EEPROMs
High Reliability
– Endurance: 100,000 Cycles
– Data Retention: 10 years
– ESD Protection: 4,000V min
•
•
CryptoMemory
128 Kbit
AT88SC12816C
Summary
•
•
•
Table 1.
Pin Configuration
Pad
VCC
GND
SCL/CLK
SDA/IO
RST
Description
Supply Voltage
Ground
Serial Clock Input
Serial Data Input/Output
Reset Input
ISO Module Contact
C1
C5
C3
C7
C2
Standard Package Pin
8
4
6
5
NC
Figure 1.
Package Options
Figure 2.
Figure 3.
Smart Card Module
VCC=C1
RST=C2
SCL/CLK=C3
NC=C4
C5=GND
C6=NC
C7=SDA/IO
C8=NC
8-lead SOIC, PDIP
NC
NC
NC
GND
1
2
3
4
8
7
6
5
VCC
NC
SCL
SDA
Rev. 5016HS–SMEM–11/08
Note: This is a summary document. A complete document is
available under NDA. For more information, please contact your
local Atmel sales office.
Description
The AT88SC12816C member of the CryptoMemory
®
family is a high-performance secure mem-
ory providing 128 Kbits of user memory with advanced security and cryptographic features built
in. The user memory is divided into 16 1-Kbyte zones, each of which may be individually set with
different security access rights or effectively combined together to provide space for one to six-
teen data files.
The AT88SC12816C provides high security, low cost, and ease of implementation without the
need for a microprocessor operating system. The embedded cryptographic engine provides for
dynamic and symmetric mutual authentication between the device and host, as well as perform-
ing stream encryption for all data and passwords exchanged between the device and host. Up to
four unique key sets may be used for these operations. The AT88SC12816C offers the ability to
communicate with virtually any smart card reader using the asynchronous T = 0 protocol (Gem-
plus Patent) defined in ISO 7816-3. Communication speeds up to 153,600 baud are supported
by utilizing ISO 7816-3 Protocol and Parameter Selection.
Through dynamic and symmetric mutual authentication, data encryption, and the use of
encrypted checksums, the AT88SC12816C provides a secure place for storage of sensitive
information within a system. With its tamper detection circuits, this information remains safe
even under attack. A 2-wire serial interface running at 1.0 MHz is used for fast and efficient com-
munications with up to 15 devices that may be individually addressed. The AT88SC12816C is
available in industry standard 8-lead packages with the same familiar pinout as 2-wire serial
EEPROMs.
Figure 2.
Block Diagram
VCC
GND
Power
Management
Authentication,
Encryption and
Certification Unit
Random
Generator
Smart Card
Applications
Embedded
Applications
Synchronous
Interface
SCL/CLK
SDA/IO
Asynchronous
ISO Interface
Data Transfer
Password
Verification
EEPROM
RST
Reset Block
Answer to Reset
Pin
Descriptions
Supply Voltage (V
CC
)
Clock (SCL/CLK)
The V
CC
input is a 2.7V to 5.5V positive voltage supplied by the host.
In the asynchronous T = 0 protocol, the SCL/CLK input is used to provide the device with a car-
rier frequency
f.
The nominal length of one bit emitted on I/O is defined as an “elementary time
unit” (ETU) and is equal to 372/f. When the synchronous protocol is used, the SCL/CLK input is
used to positive edge clock data into the device and negative edge clock data out of the device.
2
AT88SC12816C
5016HS–SMEM–11/08
AT88SC12816C
Reset (RST)
The AT88SC12816C provides an ISO 7816-3 compliant asynchronous answer to reset
sequence. When the reset sequence is activated, the device will output the data programmed
into the 64-bit answer-to-reset register. An internal pull-up on the RST input pad allows the
device to be used in synchronous mode without bonding RST. The AT88SC12816C does not
support the synchronous answer-to-reset sequence.
The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be
wired with any number of other open drain or open collector devices. An external pull-up resistor
should be connected between SDA and V
CC
. The value of this resistor and the system capaci-
tance loading the SDA bus will determine the rise time of SDA. This rise time will determine the
maximum frequency during read operations. Low value pull-up resistors will allow higher fre-
quency operations while drawing higher average power. SDA/IO information applies to both
asynchronous and synchronous protocols.
When the synchronous protocol is used, the SCL/CLK input is used to positive edge clock data
into the device and negative edge clock data out of the device.
Table 2.
DC Characteristics
Applicable over recommended operating range from V
CC
= +2.7 to 5.5V, T
AC
= -40
o
C to +85
o
C (unless otherwise noted)
Symbol
V
CC
I
CC
I
CC
I
CC
I
CC
I
SB
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
I
IL
I
IL
I
IL
I
IH
I
IH
I
IH
V
OH
V
OL
I
OH
Parameter
Supply Voltage
Supply Current (V
CC
= 5.5V)
Supply Current (V
CC
= 5.5V)
Supply Current (V
CC
= 5.5V)
Supply Current (V
CC
= 5.5V)
Standby Current (V
CC
= 5.5V)
SDA/IO Input Low Threshold
(1)
SCL/CLK Input Low Threshold
(1)
RST Input Low Threshold
(1)
SDA/IO Input High Threshold
(1)
SCL/CLK Input High Threshold
(1)
RST Input High Threshold
(1)
SDA/IO Input Low Current
SCL/CLK Input Low Current
RST Input Low Current
SDA/IO Input High Current
SCL/CLK Input High Current
RST Input High Current
SDA/IO Output High Voltage
SDA/IO Output Low Voltage
SDA/IO Output High Current
0 < V
IL
< V
CC
x 0.15
0 < V
IL
< V
CC
x 0.15
0 < V
IL
< V
CC
x 0.15
V
CC
x 0.7 < V
IH
< V
CC
V
CC
x 0.7 < V
IH
< V
CC
V
CC
x 0.7 < V
IH
< V
CC
20K ohm external pull-up
I
OL
= 1mA
V
OH
V
CC
x 0.7
0
Async READ at 3.57MHz
Async WRITE at 3.57MHz
Synch READ at 1MHz
Synch WRITE at 1MHz
V
IN
= V
CC
or GND
0
0
0
V
CC
x 0.7
V
CC
x 0.7
V
CC
x 0.7
Test Condition
Min
2.7
Typ
Max
5.5
5
5
5
5
1
V
CC
x 0.2
V
CC
x 0.2
V
CC
x 0.2
V
CC
V
CC
V
CC
15
15
50
20
100
150
V
CC
V
CC
x 0.15
20
Units
V
mA
mA
mA
mA
mA
V
V
V
V
V
V
uA
uA
uA
uA
uA
uA
V
V
uA
Serial Data
(SDA/IO)
Note: 1. V
IL
min and V
IH
max are reference only and are not tested.
3
5016HS–SMEM–11/08
Table 3.
AC Characteristics
Applicable over recommended operating range from V
CC
= +2.7 to 5.5V,
T
AC
= -40
o
C to +85
o
C, CL = 30pF (unless otherwise noted)
Symbol
f
CLK
f
CLK
f
CLK
t
R
t
F
t
R
t
F
t
AA
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
SU.STO
t
DH
t
WR
t
WR
Parameter
Async Clock Frequency (V
CC
Range: +4.5 - 5.5V)
Async Clock Frequency (V
CC
Range: +2.7 - 3.3V)
Synch Clock Frequency
Clock Duty cycle
Rise Time - I/O, RST
Fall Time - I/O, RST
Rise Time - CLK
Fall Time - CLK
Clock Low to Data Out Valid
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Stop Set-up Time
Data Out Hold Time
Write Cycle Time (at 20⋅C)
Write Cycle Time (-40
o
to +85
o
C)
200
200
10
100
200
20
5
7
Min
1
1
0
40
Max
5
4
1
60
1
1
9% x period
9% x period
35
Units
MHz
MHz
MHz
%
uS
uS
uS
uS
nS
nS
nS
nS
nS
nS
nS
mS
mS
Device
Operation For
Synchronous
Protocols
CLOCK and DATA TRANSITIONS:
The SDA pin is normally pulled high with an external device.
Data on the SDA pin may change only during SCL low time periods (see
Figure 5 on page 5).
Data changes during SCL high periods will indicate a start or stop condition as defined below.
START CONDITION:
A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (see
Figure 6 on page 6).
STOP CONDITION:
A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (see
Fig-
ure 6 on page 6).
ACKNOWLEDGE:
All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each
word. This happens during the ninth clock cycle.
MEMORY RESET:
After an interruption in protocol, power loss or system reset, any 2-wire part
can be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
4
AT88SC12816C
5016HS–SMEM–11/08
AT88SC12816C
Figure 3.
Bus Timing for 2 wire communications
SCL: Serial Clock, SDA: Serial Data I/O
Figure 4.
Write Cycle Timing:
SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
8th BIT
WORDn
ACK
t
WR
STOP
CONDITION
Note:
(1)
START
CONDITION
The write cycle time t
WR
is the time from a valid stop condition of a write sequence to the end of
the internal clear/write cycle.
Figure 5.
Data Validity
DATA
CHANGE
ALLOWED
5
5016HS–SMEM–11/08
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