DPSD64MX16XY5-DP-XX55 datasheet, PDF

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DPSD64MX16XY5-DP-XX55: DescriptionSynchronous DRAM Module, 64MX16, CMOS, PDSO54, STACKED, TSOP2-54; Categorystorage storage; File Size128KB，2 Pages; ManufacturerB&B Electronics Manufacturing Company

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DPSD64MX16XY5-DP-XX55 Overview

Synchronous DRAM Module, 64MX16, CMOS, PDSO54, STACKED, TSOP2-54

DPSD64MX16XY5-DP-XX55 Parametric

Parameter Name	Attribute value
Parts packaging code	TSOP2
package instruction	ATSOP,
Contacts	54
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PDSO-G54
memory density	1073741824 bit
Memory IC Type	SYNCHRONOUS DRAM MODULE
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	54
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
organize	64MX16
Package body material	PLASTIC/EPOXY
encapsulated code	ATSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, PIGGYBACK, THIN PROFILE
Certification status	Not Qualified
Maximum seat height	2.45 mm
self refresh	YES
surface mount	YES
technology	CMOS
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
Base Number Matches	1

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ADVANCE D COM P ON E NTS PACKAG I NG

1 Gigabit Synchronous DRAM

DPSD64MX16XY5

DESCRIPTION:

The Memory Stack™ series is a family of interchangeable memory devices. The 1 Gb SDRAM assembly utilizes the space

saving LP-Stack™ technology to increase memory density. This stack is constructed with two 512Mb (32M x 16) SDRAMs.

This 1 Gb LP-Stack™ has been designed to fit in the same footprint as the 512Mb (32M x 16) SDRAM TSOPII monolithic.

This stack allows for system upgrade without electrical or

PIN-OUT DIAGRAM

mechanical redesign, providing an alternative low cost

memory solution.

FEATURES:

•

Electrical characteristics meet semiconductor

manufacturers’ datasheets

Memory organization:

(2) 512Mb memory devices. Each device arranged

as 32M x 16 bits (8M x 16 bits x 4 banks)

Memory stack organization:

64M x 16 bits (16M x 16 bits x 4 banks)

•

JEDEC approved, 2 Rank stack pinout and footprint

(with 2 CS, 1 CKE)

Optimized for RDIMMs

IPC-A-610, class 2, manufacturing standards

Lead free manufacturing process

Package: 54-Pin TSOPII stack

VCC

DQ0

VCCQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VCCQ

DQ5

DQ6

VSSQ

DQ7

VCC

LDQM

CAS

RAS

CS0

BA0

BA1

A10

VCC

•

TOP VIEW

VSS

DQ15

VSSQ

DQ14

DQ13

VCCQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VCCQ

DQ8

VSS

CS1

UDQM

CLK

CKE

A12

A11

VSS

DQ0-DQ15

CAS

RAS

UDQM,

LDQM

CKE

CLK

CS0, CS1

CC/

CCQ/

SSQ

30A231-10

REV. C 3/03

Data In/Data Out

Column Address Strobe

Row Address Strobe

Data Write Enable

Upper & Lower

Data Input/Output Mask

Clock Enable

System Clock

Chip Selects

Power Supply/Ground

Data Output Power/Ground

512 Mb SDRAM

(8M x 16 bits x 4 banks)

BA0, BA1

Bank Select Address

CS0

RAS

CAS

UDQM

LDQM

CLK

CKE

A0-A12

BA0-BA1

(8M x 16 bits x 4 banks)

A0-A12

PIN NAMES

Row Address:

Column Address:

FUNCTIONAL BLOCK DIAGRAM

A0-A12

A0-A9

CS1

DQ0-DQ15

This document contains information on a product that is currently released to production at DPAC Technologies Corp.

DPAC reserves the right to change products or specifications herein without prior notice.

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