ADVANCE D COM P ON E NTS PACKAG I NG
1 Gigabit Synchronous DRAM
DPSD64MX16XY5
DESCRIPTION:
The Memory Stack™ series is a family of interchangeable memory devices. The 1 Gb SDRAM assembly utilizes the space
saving LP-Stack™ technology to increase memory density. This stack is constructed with two 512Mb (32M x 16) SDRAMs.
This 1 Gb LP-Stack™ has been designed to fit in the same footprint as the 512Mb (32M x 16) SDRAM TSOPII monolithic.
This stack allows for system upgrade without electrical or
PIN-OUT DIAGRAM
mechanical redesign, providing an alternative low cost
memory solution.
FEATURES:
•
•
Electrical characteristics meet semiconductor
manufacturers’ datasheets
Memory organization:
(2) 512Mb memory devices. Each device arranged
as 32M x 16 bits (8M x 16 bits x 4 banks)
Memory stack organization:
64M x 16 bits (16M x 16 bits x 4 banks)
•
•
•
•
•
JEDEC approved, 2 Rank stack pinout and footprint
(with 2 CS, 1 CKE)
Optimized for RDIMMs
IPC-A-610, class 2, manufacturing standards
Lead free manufacturing process
Package: 54-Pin TSOPII stack
VCC
DQ0
VCCQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VCCQ
DQ5
DQ6
VSSQ
DQ7
VCC
LDQM
WE
CAS
RAS
CS0
BA0
BA1
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
•
TOP VIEW
VSS
DQ15
VSSQ
DQ14
DQ13
VCCQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VCCQ
DQ8
VSS
CS1
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
1
DQ0-DQ15
CAS
RAS
WE
UDQM,
LDQM
CKE
CLK
CS0, CS1
V
CC/
V
SS
V
CCQ/
V
SSQ
30A231-10
REV. C 3/03
Data In/Data Out
Column Address Strobe
Row Address Strobe
Data Write Enable
Upper & Lower
Data Input/Output Mask
Clock Enable
System Clock
Chip Selects
Power Supply/Ground
Data Output Power/Ground
512 Mb SDRAM
(8M x 16 bits x 4 banks)
BA0, BA1
Bank Select Address
CS0
RAS
CAS
WE
UDQM
LDQM
CLK
CKE
A0-A12
BA0-BA1
(8M x 16 bits x 4 banks)
A0-A12
PIN NAMES
Row Address:
Column Address:
FUNCTIONAL BLOCK DIAGRAM
A0-A12
A0-A9
CS1
DQ0-DQ15
This document contains information on a product that is currently released to production at DPAC Technologies Corp.
DPAC reserves the right to change products or specifications herein without prior notice.
1
1 Gigabit Synchronous DRAM
DPSD64MX16XY5
ORDERING INFORMATION
DP
PREFIX
SD
TYPE
64M
MEMORY
DEPTH
X
16
X
DESIG
Y5
PACKAGE
- DP - XX
SUPPLIER
X
XXX
DESIG MEMORY
WIDTH
MFR ID MEMORY CYCLE
REVISION TIME
P12
P13
12
10
08
75
75P2
70
70P2
60
55
BLANK
n
PC100 / CL2
PC100 / CL3
12ns (83MHz)
10ns (100MHz)
8ns (125MHz)
7.5ns (133MHz) CL3
7.5ns (133MHz) CL2
7ns (143MHz) CL3
7ns (133MHz) CL2
6ns (166MHz) CL2
5.5ns (183MHz) CL3
REVISION NOT SPECIFIED
PER MANUFACTURER DIE REVISION
MANUFACTURER CODE *
SUPPLIER CODE *
STACKABLE TSOP
512 MEGABIT LVTTL BASED
MEMORY MODULE WITHOUT SUPPORT LOGIC
SYNCHRONOUS DRAM
* Contact your sales representative for supplier and manufacturer codes.
NOTE:
1. AC Parameters of base memory are unchanged from device manufacturers’ specifications.
2.
3.
4.
DC Parameters may be affected by stacking. Please refer to application note 53A004-00 for further information.
For assembly and inspection procedures, refer to application note 53A001-00.
Maximum reflow temperature recommendation is 215°C.
MECHANICAL DIAGRAM
TOP VIEW
PIN 1
1
SIDE VIEW
BOTTOM VIEW
.934±.010
[23.72±.25]
.870±.003*
[22.35±.08]*
.945 MAX.*
[22.62±.08]*
.020 [.51]
.0315 [.80]
.030 MIN.
[.76 MIN.]
END VIEW
.0805 [2.04]
.502±.008
[12.75±.20]
END VIEW DETAIL
.098 MAX.
[2.45 MAX.]
COPLANARITY:
.004 [.10] from seating plane
Inch[mm]
* Measurments are from edge of PCB.
.463 [11.76] TYP
Lead Toe-to-Toe per device datasheet
30A231-10
REV. C 3/03
DPAC Technologies
Products & Services for the Integration Age
7321 Lincoln Way, Garden Grove, CA 92841
Tel
714 898 0007
Fax
714 897 1772
www.dpactech.com Nasdaq: DPAC
2
©2003 DPAC Technologies, all rights reserved. DPAC Technologies™, Memory Stack™, System Stack™, LP-Stack™, CS-Stack™ are trademarks of DPAC Technologies Corp.
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