ry
mina
Preli
MITSUBISHI LSIs
SDRAM (Rev.1.5E)
Single Data Rate
Oct.2001
M2V56S20/ 30/ 40 TP –5,-5L, -6,-6L, -7,-7L
256M Synchronous DRAM
Some of contents are subject to change without notice.
DESCRIPTION
M2V56S20TP is a 4-bank x 16777216-word x 4-bit,
M2V56S30TP is a 4-bank x 8388608-word x 8-bit,
M2V56S40TP is a 4-bank x 4194304-word x 16-bit,
synchronous DRAM, with LVTTL interface.All inputs and outputs are referenced to the rising edge of
CLK.The M2V56S20/30/40TP achieve very high speed data rate up to 100MHz(-7) ,133MHz(-6) ,
166MHz(-5) and are suitable for main memory or graphic memory in computer systems.
FEATURES
-Single 3.3v±0.3V power supply
-Max. Clock frequency –5:PC166<3-3-3> / -6:PC133 <3-3-3> / -7:PC100 <2-2-2>
Synchronous operation referenced to clock -Fully rising edge
-Single Data Rate
-4 bank operation controlled by BA0, BA1 (Bank Address)
-/CAS latency- 2/3 (programmable)
-Burst length- 1/2/4/8/full page (programmable)
-Burst type- sequential / interleave (programmable)
-Random column access
-Auto precharge / All bank precharge controlled by A10
-8192 refresh cycles / 64ms (4 banks concurrent refresh)
-Auto refresh and Self refresh
-Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
-LVTTL Interface
-400-mil, 54-pin Thin Small Outline Package (TSOPII) with 0.8mm lead pitch
Max. Frequency
@CL2
M2V56S20/30/40TP-5/-5L
M2V56S20/30/40TP-6/-6L
M2V56S20/30/40TP-7/-7L
133MHz
100MHz
100MHz
Max. Frequency
@CL3
166MHz
133MHz
100MHz
Standard
PC133(CL2)
PC133(CL3)
PC100(CL2)
Note: The –5L/-6L/-7L is selfrefresh low power.
MITSUBISHI ELECTRIC
1
ry
mina
Preli
MITSUBISHI LSIs
SDRAM (Rev.1.5E)
Single Data Rate
Oct.2001
M2V56S20/ 30/ 40 TP –5,-5L, -6,-6L, -7,-7L
256M Synchronous DRAM
PIN CONFIGURATION
(TOP VIEW)
x4
x8
x16
Vdd
NC
VddQ
NC
DQ0
VssQ
NC
NC
VddQ
NC
DQ1
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
Vdd
Vdd
DQ0
VddQ
NC
DQ1
VssQ
NC
DQ2
VddQ
NC
DQ3
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
Vdd
Vdd
DQ0
VddQ
DQ1
DQ2
VssQ
DQ3
DQ4
VddQ
DQ5
DQ6
VssQ
DQ7
Vdd
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
Vdd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vss
DQ15
VssQ
DQ14
DQ13
VddQ
DQ12
DQ11
VssQ
DQ10
DQ9
VddQ
DQ8
Vss
NC
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
Vss
Vss
DQ7
VssQ
NC
DQ6
VddQ
NC
DQ5
VssQ
NC
DQ4
VddQ
NC
Vss
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
Vss
Vss
NC
VssQ
NC
DQ3
VddQ
NC
NC
VssQ
NC
DQ2
VddQ
NC
Vss
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
Vss
CLK
CKE
/CS
/RAS
/CAS
/WE
DQ0-15
DQM,DQMU/L
A0-12
BA0,1
Vdd
VddQ
Vss
VssQ
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O
: Output Disable / Write Mask
: Address Input
: Bank Address Input
: Power Supply
: Power Supply for Output
: Ground
: Ground for Output
MITSUBISHI ELECTRIC
400mil x 875mil 54pin 0.8mm pitch TSOP(II)
2
ry
mina
Preli
MITSUBISHI LSIs
SDRAM (Rev.1.5E)
Single Data Rate
Oct.2001
M2V56S20/ 30/ 40 TP –5,-5L, -6,-6L, -7,-7L
256M Synchronous DRAM
DQ0-3 (x4), 0-7 (x8), 0-15 (x16)
BLOCK DIAGRAM
I/O Buffer
Memory
Array
Bank #0
Memory
Array
Bank #1
Memory
Array
Bank #2
Memory
Array
Bank #3
Mode Register
Control Circuitry
Address Buffer
Clock Buffer
Control Signal Buffer
A0-12
BA0,1
CLK
CKE
/CS /RAS /CAS /WE DQMU/L
Type Designation Code
M 2
V 56 S
4
0
TP - 5
This rule is applied to only Synchronous DRAM family.
Speed Grade
5: 166MHz@CL3, 133MHz@CL2
6: 133MHz@CL3, 100MHz@CL2
7: 100MHz@CL2
Package Type TP: TSOP(II)
Process Generation
Function Reserved for Future Use
Organization 2
n
2:x4, 3:x8, 4:x16
SDRAM Data Rate Type S:Single Data Rate
Density 56: 256M bits
Interface V:LVTTL
Memory Style(DRAM)
Mitsubishi Main Designation
MITSUBISHI ELECTRIC
3
ry
mina
Preli
MITSUBISHI LSIs
SDRAM (Rev.1.5E)
Single Data Rate
Oct.2001
M2V56S20/ 30/ 40 TP –5,-5L, -6,-6L, -7,-7L
256M Synchronous DRAM
PIN FUNCTION
CLK
Input
Master Clock: All other inputs are referenced to the rising edge of CLK.
Clock Enable: CKE controls internal clock. When CKE is low,internal
clock for the following cycle is ceased. CKE is also used to select auto
/self refresh. After self refresh mode is started. CKE becomes
asynchronous input. Self refresh is maintained as long as CKE is low.
Chip Select: When /CS is high, any command means No Operation
Combination of /RAS, /CAS, /WE defines basic commands.
A0-12 specify the Row/ Column Address in conjunction with BA0,1.
The Row Address is specified by A0-12.The Column Address is
specified by A0-9,11. A10 is also used to indicate precharge option.
When A10 is high at a read / write command, an auto precharge is
performed. When A10 is high at a precharge command, all banks are
precharged.
Bank Address : BA0,1 specifies one of four banks to which a command
is applied. BA0,1 must be set with ACT, PRE, READ, WRITE
commands.
Data In and Data out are referenced to the rising edge of CLK.
Din Mask / Output Disable: When DQMU/L is high in burst write, Din for
the current cycle is masked. When DQMU/L is high in burst read, Dout
is disabled at the next but one cycle.
Power supply for the memory array and peripheral circuitry.
VddQ and VssQ are supplied to the Output Buffers only.
CKE
Input
/CS
/RAS,/CAS,/WE
Input
Input
A0-12
Input
BA0,1
Input
DQ0-15
DQM
DQMU/L
Input/Output
Input
Vdd,Vss
VddQ,VssQ
Power Supply
Power Supply
MITSUBISHI ELECTRIC
4
ry
mina
Preli
MITSUBISHI LSIs
SDRAM (Rev.1.5E)
Single Data Rate
Oct.2001
M2V56S20/ 30/ 40 TP –5,-5L, -6,-6L, -7,-7L
256M Synchronous DRAM
BASIC FUNCTIONS
The M2V56S20/30/40TP provides basic functions, bank (row) activate, burst read / write, bank (row)
precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at
CLK rising edge. In addition to 3 signals, /CS,CKE and A10 are used as chip select, refresh option, and
precharge option, respectively. To know the detailed definition of commands, please see the command
truth table.
CLK
/CS
/RAS
/CAS
/WE
CKE
A10
Chip Select:L=select, H=deselect
Command
Command
Command
Refresh Option @refresh command
Precharge Option @ precharge or read/write command
define basic commands
Activate(ACT)[/RAS=L, /CAS=/WE=H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ)[/RAS=H, /CAS=L, /WE=H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10=H at this command, the bank is deactivated after the burst read (auto-
precharge,READA)
Write(WRITE[
/RAS=H, /CAS=L, /WE=L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is set by burst length. When A10=H at this command, the bank is deactivated after the burst write
(auto-precharge,
WRITEA).
Precharge(PRE)
[/RAS=L, /CAS=H, /WE=L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read
/write operation. When A10=H at this command, all banks are deactivated(precharge all,
PREA).
Auto-Refresh(REFA)
[/RAS=/CAS=L, /WE=CKE=H]
REFA command starts auto-refresh cycle. Refresh address are generated internally.After this
command, the banks are precharged automatically.
MITSUBISHI ELECTRIC
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