MPC8360VVAHFG datasheet, PDF - EEWORLD Datasheet

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MPC8360VVAHFG: Description32-BIT, 500MHz, RISC PROCESSOR, PBGA740, 37.50 X 37.50 MM, 1.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, TBGA-740; CategoryThe embedded processor and controller Microcontrollers and processors; File Size606KB，102 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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MPC8360VVAHFG Overview

32-BIT, 500MHz, RISC PROCESSOR, PBGA740, 37.50 X 37.50 MM, 1.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, TBGA-740

MPC8360VVAHFG Parametric

Parameter Name	Attribute value
Parts packaging code	BGA
package instruction	LBGA,
Contacts	740
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	66.67 MHz
External data bus width	32
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B740
length	37.5 mm
low power mode	YES
Number of terminals	740
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Certification status	Not Qualified
Maximum seat height	1.69 mm
speed	500 MHz
Maximum supply voltage	1.35 V
Minimum supply voltage	1.15 V
Nominal supply voltage	1.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	37.5 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC
Base Number Matches	1

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Freescale Semiconductor

Technical Data

Document Number: MPC8360EEC

Rev. 5, 09/2011

MPC8360E/MPC8358E

PowerQUICC II Pro Processor

Revision 2.x TBGA Silicon

Hardware Specifications

This document provides an overview of the MPC8360E/58E

PowerQUICC II Pro processor revision 2.x TBGA features, including a

block diagram showing the major functional components. This device is

a cost-effective, highly integrated communications processor that

addresses the needs of the networking, wireless infrastructure, and

telecommunications markets. Target applications include next generation

DSLAMs, network interface cards for 3G base stations (Node Bs),

routers, media gateways, and high end IADs. The device extends current

PowerQUICC II Pro offerings, adding higher CPU performance,

additional functionality, faster interfaces, and robust interworking

between protocols while addressing the requirements related to

time-to-market, price, power, and package size. This device can be used

for the control plane and also has data plane functionality.

For functional characteristics of the processor, refer to the

MPC8360E

PowerQUICC II Pro Integrated Communications Processor Reference

Manual,

Rev. 3.

To locate any updates for this document, refer to the MPC8360E product

summary page on our website listed on the back cover of this document

or contact your Freescale sales office.

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Overview

This section describes a high-level overview including features and

general operation of the MPC8360E/58E PowerQUICC II Pro processor.

A major component of this device is the e300 core, which includes

32 Kbytes of instruction and data cache and is fully compatible with the

Power Architecture™ 603e instruction set. The new QUICC Engine

module provides termination, interworking, and switching between a

Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Electrical Characteristics . . . . . . . . . . . . . . . . . . 7

Power Characteristics . . . . . . . . . . . . . . . . . . . 12

Clock Input Timing . . . . . . . . . . . . . . . . . . . . . 14

RESET Initialization . . . . . . . . . . . . . . . . . . . . 16

DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . 18

DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

UCC Ethernet Controller: Three-Speed Ethernet,

MII Management . . . . . . . . . . . . . . . . . . . . . . . 25

Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

HDLC, BISYNC, Transparent, and Synchronous

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Package and Pin Listings . . . . . . . . . . . . . . . . . 63

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

System Design Information . . . . . . . . . . . . . . . 96

Ordering Information . . . . . . . . . . . . . . . . . . . . 99

Document Revision History . . . . . . . . . . . . . 100

– 10/100 Mbps Ethernet/IEEE Std. 802.3™ CDMA/CS interface through a media-independent interface (MII,

RMII, RGMII)

– 1000 Mbps Ethernet/IEEE 802.3 CDMA/CS interface through a media-independent interface (GMII, RGMII,

TBI, RTBI) on UCC1 and UCC2

– 9.6-Kbyte jumbo frames

– ATM full-duplex SAR, up to 622 Mbps (OC-12/STM-4), AAL0, AAL1, and AAL5 in accordance ITU-T

I.363.5

– ATM AAL2 CPS, SSSAR, and SSTED up to 155 Mbps (OC-3/STM-1) Mbps full duplex (with 4 CPS packets

per cell) in accordance ITU-T I.366.1 and I.363.2

– ATM traffic shaping for CBR, VBR, UBR, and GFR traffic types compatible with ATM forum TM4.1 for up

to 64-Kbyte simultaneous ATM channels

– ATM AAL1 structured and unstructured circuit emulation service (CES 2.0) in accordance with ITU-T I.163.1

and ATM Forum af-vtoa-00-0078.000

– IMA (Inverse Multiplexing over ATM) for up to 31 IMA links over 8 IMA groups in accordance with the ATM

forum AF-PHY-0086.000 (Version 1.0) and AF-PHY-0086.001 (Version 1.1)

– ATM Transmission Convergence layer support in accordance with ITU-T I.432

– ATM OAM handling features compatible with ITU-T I.610

– PPP, Multi-Link (ML-PPP), Multi-Class (MC-PPP) and PPP mux in accordance with the following RFCs:

1661, 1662, 1990, 2686, and 3153

– IP support for IPv4 packets including TOS, TTL, and header checksum processing

– Ethernet over first mile IEEE 802.3ah

– Shim header

– Ethernet-to-Ethernet/AAL5/AAL2 inter-working

– L2 Ethernet switching using MAC address or IEEE Std. 802.1P/Q™ VLAN tags

– ATM (AAL2/AAL5) to Ethernet (IP) interworking in accordance with RFC2684 including bridging of ATM

ports to Ethernet ports

– Extensive support for ATM statistics and Ethernet RMON/MIB statistics

– AAL2 protocol rate up to 4 CPS at OC-3/STM-1 rate

– Packet over Sonet (POS) up to 622-Mbps full-duplex 124 MultiPHY

– POS hardware; microcode must be loaded as an IRAM package

– Transparent up to 70-Mbps full-duplex

– HDLC up to 70-Mbps full-duplex

– HDLC BUS up to 10 Mbps

– Asynchronous HDLC

– UART

– BISYNC up to 2 Mbps

– User-programmable Virtual FIFO size

– QUICC multichannel controller (QMC) for 64 TDM channels

— One multichannel communication controller (MCC) only on the MPC8360E supporting the following:

– 256 HDLC or transparent channels

– 128 SS7 channels

– Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces

— Two UTOPIA/POS interfaces on the MPC8360E supporting 124 MultiPHY each (optional 2*128 MultiPHY with

extended address) and one UTOPIA/POS interface on the MPC8358E supporting 31/124 MultiPHY

— Two serial peripheral interfaces (SPI); SPI2 is dedicated to Ethernet PHY management

1.SMII or SGMII media-independent interface is not currently supported.

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

•

— Eight TDM interfaces on the MPC8360E and four TDM interfaces on the MPC8358E with 1-bit mode for E3/T3

rates in clear channel

— Sixteen independent baud rate generators and 30 input clock pins for supplying clocks to UCC and MCC serial

channels (MCC is only available on the MPC8360E)

— Four independent 16-bit timers that can be interconnected as four 32-bit timers

— Interworking functionality:

– Layer 2 10/100-Base T Ethernet switch

– ATM-to-ATM switching (AAL0, 2, 5)

– Ethernet-to-ATM switching with L3/L4 support

– PPP interworking

Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP, 802.11i®, iSCSI,

and IKE processing. The security engine contains four crypto-channels, a controller, and a set of crypto execution units

(EUs).

— Public key execution unit (PKEU) supporting the following:

– RSA and Diffie-Hellman

– Programmable field size up to 2048 bits

– Elliptic curve cryptography

– F2m and F(p) modes

– Programmable field size up to 511 bits

— Data encryption standard execution unit (DEU)

– DES, 3DES

– Two key (K1, K2) or three key (K1, K2, K3)

– ECB and CBC modes for both DES and 3DES

— Advanced encryption standard unit (AESU)

— Implements the Rinjdael symmetric key cipher

— Key lengths of 128, 192, and 256 bits, two key

– ECB, CBC, CCM, and counter modes

— ARC four execution unit (AFEU)

– Implements a stream cipher compatible with the RC4 algorithm

– 40- to 128-bit programmable key

— Message digest execution unit (MDEU)

– SHA with 160-, 224-, or 256-bit message digest

– MD5 with 128-bit message digest

– HMAC with either SHA or MD5 algorithm

— Random number generator (RNG)

— Four crypto-channels, each supporting multi-command descriptor chains

– Static and/or dynamic assignment of crypto-execution units via an integrated controller

– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes

— Storage/NAS XOR parity generation accelerator for RAID applications

Dual DDR SDRAM memory controllers on the MPC8360E and a single DDR SDRAM memory controller on the

MPC8358E

— Programmable timing supporting both DDR1 and DDR2 SDRAM

— On the MPC8360E, the DDR buses can be configured as two 32-bit buses or one 64-bit bus; on the MPC8358E,

the DDR bus can be configured as a 32- or 64-bit bus

— 32- or 64-bit data interface, up to 333 MHz (for the MPC8360E) and 266 MHz (for the MPC8358E) data rate

— Four banks of memory, each up to 1 Gbyte

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

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