PCF8562
Universal LCD driver for low multiplex rates
Rev. 3 — 2 December 2008
Product data sheet
1. General description
The PCF8562 is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD) with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 32 segments. The PCF8562
is compatible with most microprocessors or microcontrollers and communicates via a
two-line bidirectional I
2
C-bus. Communication overheads are minimized by a display RAM
with auto-incremented addressing, by hardware subaddressing and by display memory
switching (static and duplex drive modes).
AEC-Q100 compliant (PCF8562TT/S400) for automotive applications.
2. Features
I
I
I
I
I
Single chip LCD controller and driver
Selectable backplane drive configuration: static or 2, 3, 4 backplane multiplexing
Selectable display bias configuration: static,
1
⁄
2
or
1
⁄
3
Internal LCD bias generation with voltage-follower buffers
32 segment drives:
N
Up to sixteen 7-segment numeric characters
N
Up to eight 14-segment alphanumeric characters
N
Any graphics of up to 128 elements
32
×
4-bit RAM for display data storage
Auto-incremented display data loading across device subaddress boundaries
Display memory bank switching in static and duplex drive modes
Versatile blinking modes
Independent supplies possible for LCD and logic voltages
Wide power supply range: from 1.8 V to 5.5 V
Wide logic LCD supply range:
N
From 2.5 V for low-threshold LCDs
N
Up to 6.5 V for guest-host LCDs and high-threshold twisted nematic LCDs
Low power consumption
400 kHz I
2
C-bus interface
No external components
Manufactured in silicon gate CMOS process
I
I
I
I
I
I
I
I
I
I
I
NXP Semiconductors
PCF8562
Universal LCD driver for low multiplex rates
3. Ordering information
Table 1.
Ordering information
Package
Name
PCF8562TT/2
PCF8562TT/S400/2
Description
Version
TSSOP48 plastic thin shrink small outline package; 48 leads; SOT362-1
body width 6.1 mm
TSSOP48 plastic thin shrink small outline package; 48 leads; SOT362-1
body width 6.1 mm
Type number
4. Marking
Table 2.
Marking codes
Marking code
PCF8562TT
PCF8562TT
Type number
PCF8562TT/2
PCF8562TT/S400/2
PCF8562_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 3 — 2 December 2008
2 of 36
NXP Semiconductors
PCF8562
Universal LCD driver for low multiplex rates
5. Block diagram
BP0 BP2 BP1 BP3
22
V
LCD
21
23
24
25
S0 to S31
26 to 48,
1 to 9
DISPLAY SEGMENT OUTPUTS
BACKPLANE
OUTPUTS
LCD
VOLTAGE
SELECTOR
DISPLAY
CONTROLLER
DISPLAY REGISTER
V
SS
20
LCD BIAS
GENERATOR
OUTPUT BANK SELECT
AND BLINK CONTROL
CLK
SYNC
13
CLOCK SELECT
12
AND TIMING
BLINKER
TIMEBASE
PCF8562
DISPLAY
RAM
40
×
4-BIT
OSC
V
DD
SCL
SDA
15
14
11
10
OSCILLATOR
POWER-ON
RESET
COMMAND
DECODER
WRITE DATA
CONTROL
DATA POINTER AND
AUTO INCREMENT
INPUT
FILTERS
I
2
C-BUS
CONTROLLER
19
SA0
SUBADDRESS
COUNTER
16
A0
A1
17
A2
001aac262
18
Fig 1.
Block diagram of PCF8562
PCF8562_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 3 — 2 December 2008
3 of 36
NXP Semiconductors
PCF8562
Universal LCD driver for low multiplex rates
6. Pinning information
6.1 Pinning
S23
S24
S25
S26
S27
S28
S29
S30
S31
1
2
3
4
5
6
7
8
9
48 S22
47 S21
46 S20
45 S19
44 S18
43 S17
42 S16
41 S15
40 S14
39 S13
38 S12
37 S11
36 S10
35 S9
34 S8
33 S7
32 S6
31 S5
30 S4
29 S3
28 S2
27 S1
26 S0
25 BP3
001aac263
SDA 10
SCL 11
SYNC 12
CLK 13
V
DD
14
OSC 15
A0 16
A1 17
A2 18
SA0 19
V
SS
20
V
LCD
21
BP0 22
BP2 23
BP1 24
PCF8562TT
Top view. For mechanical details, see
Figure 20.
Fig 2.
Pinning diagram for PCF8562
6.2 Pin description
Table 3.
Symbol
SDA
SCL
SYNC
CLK
V
DD
OSC
A0 to A2
SA0
V
SS
Pin description
Pin
10
11
12
13
14
15
16 to 18
19
20
Description
I
2
C-bus serial data input and output
I
2
C-bus serial clock input
cascade synchronization input or output
external clock input or output
supply voltage
internal oscillator enable input
subaddress inputs
I
2
C-bus address input; bit 0
ground supply voltage
PCF8562_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 3 — 2 December 2008
4 of 36
NXP Semiconductors
PCF8562
Universal LCD driver for low multiplex rates
Pin description
…continued
Pin
21
22 to 25
26 to 48,
1 to 9
Description
LCD supply voltage
LCD backplane outputs
LCD segment outputs
Table 3.
Symbol
V
LCD
BP0 to BP3
S0 to S22,
S23 to S31
7. Functional description
The PCF8562 is a versatile peripheral device designed to interface any
microprocessor or microcontroller with a wide variety of LCDs. It can directly drive any
static or multiplexed LCD containing up to four backplanes and up to 32 segments.
The possible display configurations of the PCF8562 depend on the number of active
backplane outputs required. A selection of display configurations is shown in
Table 4.
All
of these configurations can be implemented in the typical system shown in
Figure 3.
Table 4.
Display configurations
7-segment numeric
14-segment numeric
Characters Indicator
symbols
8
6
4
2
16
12
8
4
128 dots (4
×
32)
96 dots (3
×
32)
64 dots (2
×
32)
32 dots (1
×
32)
Dot matrix
Number of:
Backplanes Segments Digits Indicator
symbols
4
3
2
1
128
96
64
32
16
12
8
4
16
12
8
4
V
DD
R
≤
t
r
2C
b
SDA 10
SCL
OSC
11
15
16
A0
V
DD
14
V
LCD
21
32 segment drives
LCD PANEL
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
PCF8562
4 backplanes
17
A1
18
A2
19
20
(up to 128
elements)
SA0 V
SS
001aac264
V
SS
The resistance of the power lines must be kept to a minimum.
Fig 3.
Typical system configuration
The host microprocessor or microcontroller maintains the 2-line I
2
C-bus communication
channel with the PCF8562. The internal oscillator is enabled by connecting
pin OSC to pin V
SS
. The appropriate biasing voltages for the multiplexed LCD waveforms
are generated internally. The only other connections required to complete the system are
to the power supplies (V
DD
, V
SS
and V
LCD
) and the LCD panel chosen for the application.
7.1 Power-on reset
At power-on the PCF8562 resets to the following starting conditions:
PCF8562_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 3 — 2 December 2008
5 of 36
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