PCK953
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL
clock driver
Rev. 05 — 9 October 2008
Product data sheet
1. General description
The PCK953 is a 3.3 V compatible, PLL-based clock driver device targeted for high
performance clock tree designs. With output frequencies of up to 125 MHz, and output
skews of 100 ps, the PCK953 is ideal for the most demanding clock tree designs. The
devices employ a fully differential PLL design to minimize cycle-to-cycle and phase jitter.
The PCK953 has a differential LVPECL reference input, along with an external feedback
input. These features make the PCK953 ideal for use as a zero delay, low skew fan-out
buffer. The device performance has been tuned and optimized for zero delay performance.
The MR/OE input pin will reset the internal counters and 3-state the output buffers when
driven HIGH.
The PCK953 is fully 3.3 V compatible and requires no external loop filter components. All
control inputs accept LVCMOS or LVTTL compatible levels, while the outputs provide
LVCMOS levels with the ability to drive terminated 50
Ω
transmission lines. For series
terminated 50
Ω
lines, each of the PCK953 outputs can drive two traces, giving the device
an effective fan-out of 1 : 18. The device is packaged in a 7 mm
×
7 mm 32-lead LQFP
package to provide the optimum combination of board density and performance.
2. Features
I
I
I
I
I
I
I
Fully integrated PLL
Output frequency up to 125 MHz in PLL mode
Outputs disable in high-impedance
LQFP32 packaging
55 ps cycle-to-cycle jitter typical
9 mA quiescent current typical
60 ps static phase offset typical
NXP Semiconductors
PCK953
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
3. Ordering information
Table 1.
Ordering information
Package
Name
PCK953BD
PCK953BD/G
LQFP32
Description
plastic low profile quad flat package; 32 leads; body 7
×
7
×
1.4 mm
Version
SOT358-1
Type number
Also refer to
Table 8 “Packing information”.
4. Functional diagram
QFB
PECL_CLK
PECL_CLK
FB_CLK
VCO_SEL
BYPASS
MR/OE
PLL_EN
002aae138
PHASE
DETECTOR
LPF
VCO
200 MHz
to 500 MHz
7
÷
2
÷
4
Q0 to Q6
Q7
Fig 1.
Functional diagram
5. Pinning information
5.1 Pinning
32 VCO_SEL
31 BYPASS
30 PLL_EN
29 GNDO
V
CCA
FB_CLK
n.c.
n.c.
n.c.
n.c.
GNDI
PECL_CLK
1
2
3
4
5
6
7
8
MR/OE 10
V
CCO
11
Q7 12
GNDO 13
Q6 14
V
CCO
15
Q5 16
9
25 GNDO
24 Q1
23 V
CCO
22 Q2
21 GNDO
20 Q3
19 V
CCO
18 Q4
17 GNDO
002aae137
27 V
CCO
28 QFB
PCK953BD
PCK953BD/G
Fig 2.
PCK953_5
Pin configuration for LQFP32
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 9 October 2008
PECL_CLK
26 Q0
2 of 15
NXP Semiconductors
PCK953
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
5.2 Pin description
Table 2.
Symbol
V
CCA
FB_CLK
n.c.
GNDI
PECL_CLK
PECL_CLK
MR/OE
V
CCO
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
GNDO
QFB
PLL_EN
BYPASS
VCO_SEL
Pin description
Pin
1
2
3, 4, 5, 6
7
8
9
10
Description
Analog supply voltage. See
Section 11 “Application information”
for
design and layout considerations.
Feedback clock input (CMOS) to comparator/phase detector.
Not connected.
Ground pin associated with input circuitry.
LVPECL reference clock input, true.
LVPECL reference clock input, complementary.
Master reset/output enable input. See
Table 3 “Function selection”.
11, 15, 19, Supply voltage pins associated with output driver circuitry.
23, 27
12
14
16
18
20
22
24
26
13, 17, 21, Ground pins associated with output driver circuitry.
25, 29
28
30
31
32
Buffered clock output intended to be fed to feedback pin FB_CLK.
PLL enable input pin. See
Table 3 “Function selection”.
Bypass input pin. See
Table 3 “Function selection”.
VCO select input pin. See
Table 3 “Function selection”.
Buffered clock outputs (CMOS).
6. Functional description
Refer to
Figure 1 “Functional diagram”.
6.1 Function selection
Table 3.
Pin
BYPASS
MR/OE
VCO_SEL
PLL_EN
Function selection
Value
1
0
1
0
1
0
1
0
PCK953_5
Function
PLL enabled
PLL bypass
outputs disabled
outputs enabled
divide-by-2
divide-by-1
select VCO
select PECL_CLK
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 9 October 2008
3 of 15
NXP Semiconductors
PCK953
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CC
V
I
I
I
T
stg
Parameter
supply voltage
input voltage
input current
storage temperature
Conditions
Min
−0.3
−0.3
-
−40
Max
+4.6
V
DD
+ 0.3
±20
+125
Unit
V
V
mA
°C
8. Static characteristics
Table 5.
Static characteristics
T
amb
= 0
°
C to 70
°
C; V
CC
= 3.3 V
±
5 %, unless specified otherwise.
Symbol
V
IH
V
IL
V
i(p-p)
V
cm
V
OH
V
OL
I
I
C
i
C
PD
I
CC
I
CCPLL
[1]
[2]
Parameter
HIGH-level input voltage
LOW-level input voltage
peak-to-peak input voltage
common-mode voltage
HIGH-level output voltage
LOW-level output voltage
input current
input capacitance
power dissipation capacitance
maximum quiescent supply current
maximum PLL supply current
Conditions
LVCMOS inputs
LVCMOS inputs
PECL_CLK
PECL_CLK
I
OH
=
−20
mA
I
OL
= 20 mA
[1]
[2]
[2]
Min
2.0
-
300
V
CC
−
1.5
2.4
-
-
-
Typ
-
-
-
-
-
-
-
-
25
9
9
Max
3.6
0.8
1000
V
CC
−
0.6
-
0.5
±75
4
-
20
20
Unit
V
V
mV
mV
V
V
µA
pF
pF
mA
mA
per output
all V
CC
pins
V
CCA
pin only
-
-
-
V
cm
is the difference from the most positive side of the differential input signal. Normal operation is obtained when the HIGH input is
within the V
cm
range and the input swing lies within the V
i(p-p)
specification.
The PCK953 outputs can drive series or parallel terminated 50
Ω
(or 50
Ω
to 0.5V
CC
) transmission lines on the incident edge (see
Section 11 “Application information”).
PCK953_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 9 October 2008
4 of 15
NXP Semiconductors
PCK953
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
9. Dynamic characteristics
Table 6.
Dynamic characteristics
T
amb
= 0
°
C to 70
°
C; V
CC
= 3.3 V
±
5 %; unless specified otherwise.
Symbol
t
r(o)
t
f(o)
δ
o
t
sk(o)
f
VCO
f
o(max)
Parameter
output rise time
output fall time
output duty cycle
output skew time
PLL VCO lock range
maximum output frequency
PLL mode; VCO_SEL = 1
PLL mode; VCO_SEL = 0
Bypass mode
t
pd
(lock)
t
pd
(bypass)
t
PLZ-HZ
t
PZL
t
jit(cc)
t
lock
input to EXT_FB delay (with
PLL locked)
input to Qn delay
output disable time
output enable time
cycle-to-cycle jitter time
maximum PLL lock time
peak-to-peak
f
ref
= 50 MHz
PLL bypassed
output-to-output; relative to QFB
Conditions
0.8 V to 2.0 V
0.8 V to 2.0 V
Min
0.30
0.30
45
-
120
20
35
-
−75
3
-
-
-
-
Typ
0.55
0.55
50
-
-
-
-
-
-
5.2
-
-
55
0.01
Max
0.8
0.8
55
100
500
100
125
225
+125
7
7
6
100
10
Unit
ns
ns
%
ps
MHz
MHz
MHz
MHz
ps
ns
ns
ns
ps
ms
10. PLL input reference characteristics
Table 7.
PLL input reference characteristics
T
amb
= 0
°
C to 70
°
C.
Maximum and minimum input reference is limited by the VCO lock range and the feedback divider.
Symbol
f
ref
f
refDC
Parameter
reference input frequency
reference input duty cycle
Conditions
Min
20
25
Typ
-
-
Max
125
75
Unit
MHz
%
PCK953_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 9 October 2008
5 of 15
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