PDI1284P11
3.3 V parallel interface transceiver/buffer
Rev. 03 — 25 August 2008
Product data sheet
1. General description
The PDI1284P11 parallel interface chip is designed to provide an asynchronous, 8-bit,
bidirectional, parallel interface for personal computers. The PDI1284P11 includes all 19
signal lines defined by the IEEE 1284 interface specification for Byte, Nibble, EPP, and
ECP modes. The PDI1284P11 is designed for hosts or peripherals operating at 3.3 V to
interface 3.3 V or 5.0 V devices.
The eight transceiver pairs (A/B 1 to 8) allow data transmission from the A-bus to the
B-bus, or from the B-bus to the A-bus, depending on the state of the direction pin DIR.
The B-bus and the Y9 to Y13 lines have either totem pole or resistor pull-up outputs,
depending on the state of the high drive enable pin HD. The A-bus has only totem pole
style outputs. All inputs are TTL compatible with at least 400 mV of input hysteresis at
V
CC
= 3.3 V.
2. Features
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Asynchronous operation
8-bit transceivers
Six additional buffer/driver lines peripheral to cable
Five additional control lines from cable
5 V tolerant
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
Latch-up current protection exceeds 500 mA per JEDEC Std 19
Input hysteresis
Low-noise operation
IEEE 1284 compliant level 1 and 2
Overvoltage protection on B/Y side for off-state
A side 3-state option
B side active or resistive pull-up option
Cable side supply voltage for 5 V or 3 V operation
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NXP Semiconductors
PDI1284P11
3.3 V parallel interface transceiver/buffer
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
PDI1284P11DL
PDI1284P11DGG
0
°C
to 70
°C
0
°C
to 70
°C
SSOP48
TSSOP48
Description
plastic shrink small outline package; 48 leads;
body width 7.5 mm
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
Version
SOT370-1
SOT362-1
Type number
PDI1284P11_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 25 August 2008
2 of 16
NXP Semiconductors
PDI1284P11
3.3 V parallel interface transceiver/buffer
4. Functional diagram
HD
HD
CNTL
HD
HD
HD
HD
HD
HD
DIR
OEA
Y9
Y10
Y11
Y12
Y13
A9
A10
A11
A12
A13
A1
CNTL
HD
A2
CNTL
HD
A3
CNTL
HD
A4
CNTL
HD
A5
CNTL
HD
A6
CNTL
HD
A7
CNTL
HD
A8
CNTL
PLHI
A14
A15
A16
A17
HLHO
001aai290
B1
B2
B3
B4
B5
B6
B7
B8
HD
PLHO
C14
C15
C16
C17
HLHI
Fig 1.
Logic symbol
PDI1284P11_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 25 August 2008
3 of 16
NXP Semiconductors
PDI1284P11
3.3 V parallel interface transceiver/buffer
5. Pinning information
5.1 Pinning
HD
A9
A10
A11
A12
A13
V
CC
A1
A2
1
2
3
4
5
6
7
8
9
48 DIR
47 Y9
46 Y10
45 Y11
44 Y12
43 Y13
42 V
CC(B)
41 B1
40 B2
39 GND
38 B3
37 B4
36 B5
35 B6
34 OEA
33 B7
32 B8
31 V
CC(B)
30 PLHO
29 C14
28 C15
27 C16
26 C17
25 HLHI
001aai291
GND 10
A3 11
A4 12
A5 13
A6 14
GND 15
A7 16
A8 17
V
CC
18
PLHI 19
A14 20
A15 21
A16 22
A17 23
HLHO 24
PDI1284P11
Fig 2.
Pin configuration
5.2 Pin description
Table 2.
Symbol
HD
A1 to A8
B1 to B8
A9 to A13
Y9 to Y13
C14 to C17
A14 to A17
V
CC
GND
PLHI
PDI1284P11_3
Pin description
Pin
1
8, 9, 11, 12, 13,
14, 16, 17
41, 40, 38, 37,
36, 35, 33, 32
2, 3, 4, 5, 6
29, 28, 27, 26
20, 21, 22, 23
7, 18
10, 15, 39
19
Description
high drive enable/disable input
data input/output
IEEE 1284 standard output/input
[1]
data input
control input (cable)
[1]
control output (peripheral)
supply voltage
ground (0 V)
peripheral logic high input (peripheral)
© NXP B.V. 2008. All rights reserved.
47, 46, 45, 44, 43 IEEE 1284 standard output
[1]
Product data sheet
Rev. 03 — 25 August 2008
4 of 16
NXP Semiconductors
PDI1284P11
3.3 V parallel interface transceiver/buffer
Table 2.
Symbol
HLHO
HLHI
PLHO
V
CC(B)
OEA
DIR
[1]
Pin description
…continued
Pin
24
25
30
31, 42
34
48
Description
host logic high output (cable)
host logic high input (cable)
peripheral logic high output (cable)
supply voltage B (cable side 3 V/5 V)
A side output enable input (active LOW)
direction selection input
Pin with pull-up resistor to load cable.
6. Functional description
6.1 Function selection
Table 3.
DIR
X
X
X
X
X
X
H
H
L
L
L
[1]
Function table
[1]
OEA
X
X
X
X
X
X
X
X
L
H
H
HD
X
X
L
H
L
H
L
H
X
X
X
Input
C14 to C17
HLHI
A9 to A13
A9 to A13
PLHI
PLHI
A1 to A8
A1 to A8
B1 to B8
-
B1 to B8
Output
A14 to A17
HLHO
Y9 to Y13
Y9 to Y13
PLHO
PLHO
B1 to B8
B1 to B8
A1 to A8
A1 to A8
-
Output type
TP
TP
RP
TP
OC
TP
RP
TP
TP
Z
[2]
RP
[2]
An = side driving internal IC;
Bn = side driving external cable (bidirectional);
Cn = side receiving control signals from external cable;
H = HIGH voltage level;
L = LOW voltage level;
OC = Open Collector;
X = don’t care (control signals in);
Yn = side driving external cable (unidirectional);
Z = high impedance (high-Z) or 3-state;
TP = totem pole output;
RP = resistive pull-up: 1.4 kΩ (nominal) on B/Y/C cable side and V
CC
. However, while a B/Y side output is LOW as driven by a LOW
signal on the A side, that particular B/Y side resistor is switched off to stop current drain from V
CC
through it.
[2]
When DIR = L and OEA = H, the output signal is isolated from the input signal. Signals B1 to B8 maintain a resistive pull-up of 1.4 kΩ on
the input for this mode.
PDI1284P11_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 25 August 2008
5 of 16
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