PSMN3R0-30YL
N-channel TrenchMOS logic level FET
Rev. 01 — 10 September 2008
Preliminary data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
industrial and communications applications.
1.2 Features and benefits
High efficiency due to low switching
and conduction losses
Suitable for logic level gate drive
sources
1.3 Applications
Class-D amplifiers
DC-to-DC converters
Motor control
Server power supplies
1.4 Quick reference data
Table 1.
V
DS
I
D
P
tot
Quick reference
Conditions
T
mb
= 25 °C; V
GS
= 10 V;
see
Figure 1;
T
mb
= 25 °C; see
Figure 2
[1]
Min
-
-
-
Typ
-
-
-
Max
30
100
81
Unit
V
A
W
drain-source voltage T
j
≥
25 °C; T
j
≤
150 °C
drain current
total power
dissipation
gate-drain charge
Symbol Parameter
Dynamic characteristics
Q
GD
V
GS
= 4.5 V; I
D
= 10 A;
V
DS
= 12 V; see
Figure 14;
see
Figure 15
V
GS
= 10 V; I
D
= 15 A;
T
j
= 25 °C; see
Figure 12
-
5.1
-
nC
Static characteristics
R
DSon
drain-source
on-state resistance
-
2.15
3
mΩ
[1]
Continuous current is limited by package.
NXP Semiconductors
PSMN3R0-30YL
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pin
1
2
3
4
mb
S
S
S
G
D
Pinning information
Symbol
Description
source
source
source
gate
mounting base; connected to
drain
mbb076
Simplified outline
mb
Graphic symbol
D
G
S
1 2 3 4
SOT669
(LFPAK)
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
PSMN3R0-30YL
LFPAK
Description
Version
Plastic single-ended surface-mounted package (LFPAK); SOT669
4 leads
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
V
GS
= 10 V; T
mb
= 100 °C; see
Figure
1;
V
GS
= 10 V; T
mb
= 25 °C; see
Figure 1;
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
non-repetitive drain-source
avalanche energy
[1]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Conditions
T
j
≥
25 °C; T
j
≤
150 °C
T
j
≥
25 °C; T
j
≤
150 °C; R
GS
= 20 kΩ
[1]
[1]
Min
-
-
-20
-
-
-
-
-55
-55
T
mb
= 25 °C;
t
p
≤
10 µs; pulsed; T
mb
= 25 °C
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 100 A;
V
sup
≤
30 V; R
GS
= 50
Ω;
unclamped
[1]
-
-
-
Max
30
30
20
88
100
497
81
150
150
100
497
75
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
t
p
≤
10 µs; pulsed; T
mb
= 25 °C; see
Figure 3
T
mb
= 25 °C; see
Figure 2
Source-drain diode
Avalanche ruggedness
Continuous current is limited by package.
PSMN3R0-30YL_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 10 September 2008
2 of 13
NXP Semiconductors
PSMN3R0-30YL
N-channel TrenchMOS logic level FET
I
D
(A)
120
100
(1)
140
003aac568
120
P
der
(%)
80
03aa15
80
60
40
40
20
0
0
50
100
150
T
mb
(°C)
200
0
0
50
100
150
T
mb
(°C)
200
Fig 1. Continuous drain current as a function of
mounting base temperature
10
3
I
D
(A)
10
2
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
003aac577
10
μs
Limit R
DSon
= V
DS
/ I
D
100
μs
10
1 ms
DC
1
10 ms
100 ms
10
-1
10
-1
1
10
V
DS
(V)
10
2
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN3R0-30YL_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 10 September 2008
3 of 13
NXP Semiconductors
PSMN3R0-30YL
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance
from junction to
mounting base
Conditions
see
Figure 4
Min
-
Typ
-
Max
1.5
Unit
K/W
10
Z
th(j-mb)
(K/W)
1
δ
= 0.5
0.2
10
-1
0.1
0.05
0.02
t
p
P
003aac573
δ
=
t
p
T
t
T
single shot
10
-2
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
t
p
(s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN3R0-30YL_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 10 September 2008
4 of 13
NXP Semiconductors
PSMN3R0-30YL
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
V
(BR)DSS
V
GS(th)
Characteristics
Parameter
drain-source
breakdown voltage
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
Min
30
27
1.3
0.65
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
DS
= 12 V; see
Figure 14;
see
Figure 15
V
DS
= 12 V; V
GS
= 0 V; f = 1 MHz;
T
j
= 25 °C; see
Figure 16
-
-
-
-
V
DS
= 12 V; R
L
= 0.5
Ω;
V
GS
= 4.5 V;
R
G(ext)
= 4.7
Ω
-
-
-
-
Typ
-
-
1.7
-
-
-
-
-
-
2.98
-
2.15
0.55
45.8
43
21
7.02
5.1
4.74
2.28
2.37
2822
615
260
34
58
50
21
Max
-
-
2.15
-
2.45
1
100
100
100
4.8
5.2
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
V
V
V
V
V
µA
µA
nA
nA
mΩ
mΩ
mΩ
Ω
nC
nC
nC
nC
nC
nC
nC
V
pF
pF
pF
ns
ns
ns
ns
Static characteristics
gate-source threshold I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C; see
voltage
Figure 10;
see
Figure 11
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 150 °C; see
Figure 10
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C; see
Figure 10
I
DSS
I
GSS
R
DSon
drain leakage current
gate leakage current
drain-source on-state
resistance
V
DS
= 30 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 30 V; V
GS
= 0 V; T
j
= 150 °C
V
GS
= 16 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -16 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 4.5 V; I
D
= 15 A; T
j
= 25 °C; see
Figure 12
V
GS
= 10 V; I
D
= 15 A; T
j
= 150 °C; see
Figure 13
V
GS
= 10 V; I
D
= 15 A; T
j
= 25 °C; see
Figure 12
R
G
Q
G(tot)
gate resistance
total gate charge
f = 1 MHz
I
D
= 10 A; V
DS
= 12 V; V
GS
= 10 V; see
Figure 14;
see
Figure 15
I
D
= 0 A; V
DS
= 0 V; V
GS
= 10 V
I
D
= 10 A; V
DS
= 12 V; V
GS
= 4.5 V; see
Figure 14
Dynamic characteristics
Q
GS
Q
GD
Q
GS(th)
Q
GS(th-pl)
V
GS(pl)
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
PSMN3R0-30YL_1
gate-source charge
gate-drain charge
pre-threshold
gate-source charge
post-threshold
gate-source charge
gate-source plateau
voltage
input capacitance
output capacitance
reverse transfer
capacitance
turn-on delay time
rise time
turn-off delay time
fall time
I
D
= 10 A; V
DS
= 12 V; V
GS
= 4.5 V; see
Figure 14;
see
Figure 15
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 10 September 2008
5 of 13
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