PH3330L
N-channel TrenchMOS logic level FET
Rev. 02 — 22 October 2008
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
High efficiency due to low switching
and conduction losses
Suitable for logic level gate drive
sources
1.3 Applications
DC-to-DC converters
Notebook computers
Switched-mode power supplies
Voltage regulators
1.4 Quick reference data
Table 1.
V
DS
I
D
P
tot
Quick reference
Conditions
T
mb
= 25 °C; V
GS
= 10 V;
see
Figure 1;
see
Figure 3
T
mb
= 25 °C; see
Figure 2
Min
-
-
-
Typ
-
-
-
Max
30
100
62.5
Unit
V
A
W
drain-source voltage T
j
≥
25 °C; T
j
≤
150 °C
drain current
total power
dissipation
gate-drain charge
Symbol Parameter
Dynamic characteristics
Q
GD
V
GS
= 4.5 V; I
D
= 25 A;
V
DS
= 12 V; see
Figure 12;
see
Figure 13
V
GS
= 10 V; I
D
= 25 A;
T
j
= 25 °C; see
Figure 10;
see
Figure 11
-
6.9
-
nC
Static characteristics
R
DSon
drain-source
on-state resistance
-
2.3
3.3
mΩ
NXP Semiconductors
PH3330L
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pin
1
2
3
4
mb
S
S
S
G
D
Pinning information
Symbol
Description
source
source
source
gate
mounting base; connected to
drain
mbb076
Simplified outline
mb
Graphic symbol
D
G
S
1 2 3 4
SOT669
(LFPAK)
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
PH3330L
LFPAK
plastic single-ended surface-mounted package (LFPAK); 4 leads
Version
SOT669
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
V
GS
= 10 V; T
mb
= 25 °C; see
Figure 1;
see
Figure
3
V
GS
= 10 V; T
mb
= 100 °C; see
Figure 1
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
T
mb
= 25 °C
t
p
≤
10 µs; pulsed; T
mb
= 25 °C
t
p
≤
10 µs; pulsed; T
mb
= 25 °C; see
Figure 3
T
mb
= 25 °C; see
Figure 2
Conditions
T
j
≥
25 °C; T
j
≤
150 °C
T
j
≥
25 °C; T
j
≤
150 °C; R
GS
= 20 kΩ
Min
-
-
-20
-
-
-
-
-55
-55
-
-
-
Max
30
30
20
100
54.2
300
62.5
150
150
52
208
245
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
Avalanche ruggedness
non-repetitive
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 70 A; V
sup
≤
30 V;
drain-source avalanche t
p
= 0.15 ms; R
GS
= 50
Ω;
unclamped
energy
PH3330L_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 22 October 2008
2 of 13
NXP Semiconductors
PH3330L
N-channel TrenchMOS logic level FET
120
I
der
(%)
80
03aa23
120
P
der
(%)
80
03aa15
40
40
0
0
50
100
150
T
mb
(°C)
200
0
0
50
100
150
T
mb
(°C)
200
Fig 1.
Normalized continuous drain current as a
function of mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
003aab259
10
3
I
D
(A)
Limit R
DSon
= V
DS
/ I
D
t
p
= 10
μ
s
100
μ
s
1 ms
10
2
10
DC
10 ms
100 ms
1
10
-1
1
10
V
DS
(V)
10
2
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PH3330L_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 22 October 2008
3 of 13
NXP Semiconductors
PH3330L
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
Conditions
Min
-
Typ
-
Max
2
Unit
K/W
thermal resistance from see
Figure 4
junction to mounting
base
10
Z
th(j-mb)
(K/W)
1
δ =
0.5
0.2
0.1
0.05
10
-1
0.02
single pulse
t
p
T
P
003aab260
δ
=
t
p
T
t
10
-2
10
-5
10
-4
10
-3
10
-2
10
-1
1
t
p
(s)
10
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PH3330L_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 22 October 2008
4 of 13
NXP Semiconductors
PH3330L
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
V
(BR)DSS
V
GS(th)
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C; see
Figure 8;
see
Figure 9
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 150 °C; see
Figure 8;
see
Figure 9
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C; see
Figure 8;
see
Figure 9
I
DSS
I
GSS
R
DSon
drain leakage current
gate leakage current
drain-source on-state
resistance
V
DS
= 30 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 30 V; V
GS
= 0 V; T
j
= 150 °C
V
GS
= 16 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -16 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 10 V; I
D
= 25 A; T
j
= 25 °C; see
Figure 10;
see
Figure 11
V
GS
= 10 V; I
D
= 25 A; T
j
= 150 °C; see
Figure 11;
see
Figure 10
V
GS
= 4.5 V; I
D
= 25 A; T
j
= 25 °C; see
Figure 10;
see
Figure 11
R
G
Q
G(tot)
gate resistance
total gate charge
f = 1 MHz
I
D
= 25 A; V
DS
= 12 V; V
GS
= 4.5 V; see
Figure 12;
see
Figure 13
I
D
= 0 A; V
DS
= 0 V; V
GS
= 4.5 V
Q
GS
Q
GS1
Q
GS2
Q
GD
V
GS(pl)
C
iss
gate-source charge
pre-threshold
gate-source charge
post-threshold
gate-source charge
gate-drain charge
gate-source plateau
voltage
input capacitance
I
D
= 25 A; V
DS
= 12 V; see
Figure 12;
see
Figure 13
V
DS
= 12 V; V
GS
= 0 V; f = 1 MHz;
T
j
= 25 °C; see
Figure 14
V
DS
= 0 V; V
GS
= 0 V; f = 1 MHz;
T
j
= 25 °C
C
oss
C
rss
output capacitance
reverse transfer
capacitance
V
DS
= 12 V; V
GS
= 0 V; f = 1 MHz;
T
j
= 25 °C; see
Figure 14
I
D
= 25 A; V
DS
= 12 V; V
GS
= 4.5 V; see
Figure 12;
see
Figure 13
Dynamic characteristics
-
-
-
-
-
-
-
-
-
-
-
30.5
28.5
15.4
7.7
7.7
6.9
3.4
4840
5380
960
410
-
-
-
-
-
-
-
-
-
-
-
nC
nC
nC
nC
nC
nC
V
pF
pF
pF
pF
Min
30
27
1.3
0.8
-
-
-
-
-
-
-
-
-
Typ
-
-
1.7
-
-
-
-
-
-
2.3
4.1
3.4
0.7
Max
-
-
2.15
-
2.6
1
100
100
100
3.3
6
4.5
-
Unit
V
V
V
V
V
µA
µA
nA
nA
mΩ
mΩ
mΩ
Ω
Static characteristics
PH3330L_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 22 October 2008
5 of 13
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