DATASHEET
ISL8036, ISL8036A
Dual 3A 1MHz/2.5MHz High Efficiency Synchronous Buck Regulator
ISL8036, ISL8036A are integrated power controllers rated for
dual 3A output current or current sharing operation with a
1MHz (ISL8036)/2.5MHz (ISL8036A) step-down regulator,
which is ideal for any low power low-voltage applications. The
channels are 180° out-of-phase for input RMS current and EMI
reduction. It is optimized for generating low output voltages
down to 0.8V each. The supply voltage range is from 2.8V to
6V, allowing for the use of a single Li+ cell, three NiMH cells or
a regulated 5V input. The two channels are 180° out-of-phase,
and each one has a guaranteed minimum output current of
3A. They can be combined to form a single 6A output in the
current sharing mode. While in current sharing, the interleaved
PWM signals reduce input and output ripple.
The ISL8036, ISL8036A includes a pair of low ON-resistance
P-channel and N-channel internal MOSFETs to maximize
efficiency and minimize external component count. 100%
duty-cycle operation allows less than 250mV dropout voltage
at 3A each.
The ISL8036, ISL8036A offers an independent 1ms
Power-good (PG) timer at power-up. When shutdown, ISL8036,
ISL8036A discharges the output capacitor. Other features
include internal digital soft-start, enable for power sequence,
overcurrent protection, and thermal shutdown.
The ISL8036, ISL8036A is offered in a 24 Ld 4mmx4mm QFN
package with 1mm maximum height. The complete converter
occupies less than 1.5cm
2
area.
FN6853
Rev 3.00
August 17, 2012
Features
• 3A High Efficiency Synchronous Buck Regulator with up to
95% Efficiency
• 2% Output Accuracy Over-Temperature/Load/Line
• Internal Digital Soft-Start - 1.5ms
• 6A Current Sharing Mode Operation
• External Synchronization up to 6MHz
• Internal Current Mode Compensation
• Peak Current Limiting and Hiccup Mode Short Circuit
Protection
• Reverse Overcurrent Protection
Applications
• DC/DC POL Modules
• µC/µP, FPGA and DSP Power
• Plug-in DC/DC Modules for Routers and Switchers
• Test and Measurement Systems
• Li-ion Battery Power Devices
• Bar Code Reader
Related Literature
•
AN1616,
“ISL8036CRSHEVAL1Z Current Sharing 6A Low
Quiescent Current High Efficiency Synchronous Buck
Regulator”
•
AN1617,
“ISL8036DUALEVAL1Z Dual 3A Low Quiescent
Current High Efficiency Synchronous Buck Regulator”
•
AN1615,
“ISL8036ACRSHEVAL1Z Current Sharing 6A Low
Quiescent Current High Efficiency Synchronous Buck
Regulator”
•
AN1618,
“ISL8036ADUALEVAL1Z Dual 3A Low Quiescent
Current High Efficiency Synchronous Buck Regulator”
100
90
80
70
60
50
40
3.3V
OUT
- PWM
EFFICIENCY (%)
0
1
2
3
4
OUTPUT LOAD (A)
5
6
FIGURE 1. EFFICIENCY vs LOAD, 1MHz 5V
IN
PWM, T
A
= +25°C
FN6853 Rev 3.00
August 17, 2012
Page 1 of 26
ISL8036, ISL8036A
TABLE 1. COMPONENT VALUE SELECTION FOR DUAL OPERATION
V
OUT
C1
C2 (or C4)
L1 (or L2)*
R2 (or R5)
R3 (or R6)
0.8V
2x22µF
2X22µF
1.0~2.2µH
0
100k
1.2V
2x22µF
2X22µF
1.0~2.2µH
50k
100k
1.5V
2x22µF
2X22µF
1.0~2.2µH
87.5k
100k
1.8V
2x22µF
2X22µF
1.0~3.3µH
124k
100k
2.5V
2x22µF
2X22µF
1.0~3.3µH
212.5k
100k
3.3V
2x22µF
2X22µF
1.0~4.7µH
312.5k
100k
*For ISL8036A, the values used for L1 (or L2) are half the values specified above for each V
OUT
.
TABLE 2. COMPONENT VALUE SELECTION FOR CURRENT SHARING OPERATION
V
OUT
C1
C2 (or C4)
L1 (or L2)*
R2
R3
R6
C6
0.8V
2x22µF
2X22µF
1.0~2.2µH
0
100k
30k
250pF
1.2V
2x22µF
2X22µF
1.0~2.2µH
50k
100k
33k
180pF
1.5V
2x22µF
2X22µF
1.0~2.2µH
87.5k
100k
31k
150pF
1.8V
2x22µF
2X22µF
1.0~3.3µH
124k
100k
30k
150pF
2.5V
2x22µF
2X22µF
1.0~3.3µH
212.5k
100k
29k
150pF
3.3V
2x22µF
2X22µF
1.0~4.7µH
312.5k
100k
28k
150pF
*For ISL8036A, the values used for L1 (or L2) are half the values specified above for each V
OUT
.
NOTE: C5 value (22nF) is given by Equation 1 corresponding to the desired soft-start time.
TABLE 3. SUMMARY OF DIFFERENCES
PART NUMBER
ISL8036
ISL8036A
Internally fixed switching frequency F
SW
= 1MHz
Internally fixed switching frequency F
SW
= 2.5MHz
SWITCHING FREQUENCY
FN6853 Rev 3.00
August 17, 2012
Page 3 of 26
ISL8036, ISL8036A
Pin Configuration
ISL8036, ISL8036A
(24 LD QFN)
TOP VIEW
PGND2
PGND2
PGND1
PGND1
20
LX2
LX1
19
18 LX1
17 VIN1
25
PAD
16 VIN1
15 VDD
14 SS
13 EN1
7
COMP
8
NC
9
FB1
10
SGND
11
PG1
12
SYNC
24
LX2
VIN2
VIN2
EN2
PG2
FB2
1
2
3
4
5
6
23
22
21
Pin Descriptions
PIN
NUMBER
1, 24
22, 23
4
5
6
7
SYMBOL
LX2
PGND2
EN2
PG2
FB2
COMP
DESCRIPTION
Switching node connection for Channel 2. Connect to one terminal of inductor for VOUT2.
Negative supply for the power stage of Channel 2.
Regulator Channel 2 enable pin. Enable the output, VOUT2, when driven to high. Shutdown the VOUT2 and discharge
output capacitor when driven to low. Do not leave this pin floating.
1ms timer output. At power-up or EN HI, this output is a 1ms delayed Power-Good signal for the VOUT2 voltage.
The feedback network of the Channel 2 regulator. To be connected to FB1 (current sharing)
An additional external network across COMP and SGND is required to improve the loop compensation of the amplifier
channel parallel operation. The soft-start pin should be tied to the external capacitor. COMP pin is NC in dual mode
operation, using internal compensation. If SS pin is tied to CSS (without connection to VIN), external compensation is
automtaically used. Connect an external R,C network on COMP pin for parallel mode operation.
No connect pin; please tie to GND.
The feedback network of the Channel 1 regulator. FB1 is the negative input to the transconductance error amplifier.
The output voltage is set by an external resistor divider connected to FB1. With a properly selected divider, the output
voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.8V reference. There
is an internal compensation to meet a typical application. In addition, the regulator power-good and undervoltage
protection circuitry use FB1 to monitor the Channel 1 regulator output voltage.
System ground.
1ms timer output. At power-up or EN HI, this output is a 1ms delayed Power-Good signal for the VOUT1 voltage.
Connect to logic high or input voltage VIN . Connect to an external function generator for external Synchronization.
Negative edge trigger. Do not leave this pin floating. Do not tie this pin low (or to SGND).
Regulator Channel 1 enable pin. Enable the output, VOUT1, when driven to high. Shutdown the VOUT1 and discharge
output capacitor when driven to low. Do not leave this pin floating.
8
9
NC
FB1
10
11
12
13
SGND
PG1
SYNC
EN1
FN6853 Rev 3.00
August 17, 2012
Page 5 of 26
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