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1 MSPS, 12-/10-/8-Bit ADCs
in 6-Lead SOT-23
AD7476/AD7477/AD7478
FEATURES
Fast Throughput Rate: 1 MSPS
Specified for V
DD
of 2.35 V to 5.25 V
Low Power:
3.6 mW Typ at 1 MSPS with 3 V Supplies
15 mW Typ at 1 MSPS with 5 V Supplies
Wide Input Bandwidth:
70 dB SNR at 100 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface
SPI™/QSPI™/MICROWIRE™/DSP Compatible
Standby Mode: 1 A Max
6-Lead SOT-23 Package
APPLICATIONS
Battery-Powered Systems
Personal Digital Assistants
Medical Instruments
Mobile Communications
Instrumentation and Control Systems
Data Acquisition Systems
High Speed Modems
Optical Sensors
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
V
DD
V
IN
T/H
8-/10-/12-BIT
SUCCESSIVE
APPROXIMATION
ADC
SCLK
CONTROL
LOGIC
SDATA
CS
AD7476/AD7477/AD7478
GND
PRODUCT HIGHLIGHTS
The AD7476/AD7477/AD7478 are, respectively, 12-bit, 10-bit,
and 8-bit, high speed, low power, successive-approximation
ADCs. The parts operate from a single 2.35 V to 5.25 V power
supply and feature throughput rates up to 1 MSPS. The parts
contain a low noise, wide bandwidth track-and-hold amplifier
that can handle input frequencies in excess of 6 MHz.
The conversion process and data acquisition are controlled
using
CS
and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of
CS
and the conversion is also initiated at this
point. There are no pipeline delays associated with the part.
The AD7476/AD7477/AD7478 use advanced design techniques
to achieve very low power dissipation at high throughput rates.
The reference for the part is taken internally from V
DD.
This
allows the widest dynamic input range to the ADC. Thus the
analog input range for the part is 0 V to V
DD
. The conversion
rate is determined by the SCLK.
1. First 12-/10-/8-Bit ADCs in a SOT-23 Package.
2. High Throughput with Low Power Consumption.
3. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. This allows the average power consumption
to be reduced while not converting. The part also features a
shutdown mode to maximize power efficiency at lower
throughput rates. Current consumption is 1
mA
maximum
when in shutdown.
4. Reference Derived from the Power Supply.
5. No Pipeline Delay.
The parts feature a standard successive approximation ADC
with accurate control of the sampling instant via a
CS
input
and once-off conversion control.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD7476–SPECIFICATIONS
1
Parameter
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD)
3
3
(A Version: V
DD
= 2.7 V to 5.25 V, f
SCLK
= 20 MHz, f
SAMPLE
= 1 MSPS, unless otherwise
noted; S and B Versions: V
DD
= 2.35 V to 5.25 V, f
SCLK
= 12 MHz, f
SAMPLE
= 600 kSPS,
unless otherwise noted; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
S Version
1, 2
69
70
70
–78
–80
–78
–78
10
30
6.5
Unit
dB min
dB min
dB typ
dB min
dB typ
dB typ
dB typ
dB typ
dB typ
ns typ
ps typ
MHz typ
Test Conditions/Comments
f
IN
= 100 kHz Sine Wave
B Version, V
DD
= 2.4 V to 5.25 V
T
A
= 25∞C
B Version, V
DD
= 2.4 V to 5.25 V
A Version
1, 2
69
70
70
–80
–82
–78
–78
10
30
6.5
B Version
1, 2
70
71.5
71
72.5
–78
–80
–78
–78
10
30
6.5
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
3
Peak Harmonic or Spurious Noise (SFDR)
3
Intermodulation Distortion (IMD)
3
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity
3
Differential Nonlinearity
3
Offset Error
3
Gain Error
3
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
, SCLK Pin
Input Current, I
IN
,
CS
Pin
Input Capacitance, C
IN3, 5
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
3, 5
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
V
DD
I
DD
Normal Mode (Static)
Normal Mode (Operational)
Full Power-Down Mode
Power Dissipation
7
Normal Mode (Operational)
Full Power-Down
fa = 103.5 kHz, fb = 113.5 kHz
fa = 103.5 kHz, fb = 113.5 kHz
@ 3 dB
S, B Versions, V
DD
= (2.35 V to 3.6 V)
4
;
A Version, V
DD
= (2.7 V to 3.6 V)
12
±
1
±
0.75
±
0.5
±
0.5
0 to V
DD
±
1
30
2.4
1.8
0.4
0.8
±
1
±
1
10
12
±
1.5
±
0.6
–0.9/+1.5
±
0.75
±
1.5
±
1.5
12
±
1.5
±
0.6
–0.9/+1.5
±
0.75
±
2
±
2
Bits
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
V
mA
max
pF typ
V min
V min
V max
V max
mA
max
mA
typ
pF max
V min
V max
mA
max
pF max
Guaranteed No Missed Codes to 12 Bits
0 to V
DD
±
1
30
2.4
1.8
0.4
0.8
±
1
±
1
10
0 to V
DD
±
1
30
2.4
1.8
0.4
0.8
±
1
±
1
10
V
DD
– 0.2
0.4
±
10
10
V
DD
= 2.35 V
V
DD
= 3 V
V
DD
= 5 V
Typically 10 nA, V
IN
= 0 V or V
DD
V
DD
– 0.2
V
DD
– 0.2
0.4
0.4
±
10
±
10
10
10
Straight (Natural) Binary
0.8
500
350
1000
2.35/5.25
2
1
3.5
1.6
1
80
17.5
4.8
5
3
1.33
500
400
600
2.35/5.25
2
1
3
1.4
1
80
15
4.2
5
3
I
SOURCE
= 200
mA;
V
DD
= 2.35 V to 5.25 V
I
SINK
= 200
mA
1.33
500
400
600
2.35/5.25
2
1
3
1.4
1
80
15
4.2
5
3
5
6
ms
max
ns max
ns max
kSPS max
V min/max
mA typ
mA typ
mA max
mA max
mA
max
mA
max
mW max
mW max
mW
max
mW
max
16 SCLK Cycles
Full-Scale Step Input
Sine Wave Input
£100
kHz
See Serial Interface Section
Digital I/Ps = 0 V or V
DD
V
DD
= 4.75 V to 5.25 V. SCLK On or Off
V
DD
= 2.35 V to 3.6 V. SCLK On or Off
V
DD
= 4.75 V to 5.25 V; f
SAMPLE
= f
SAMPLE
MAX
6
V
DD
= 2.35 V to 3.6 V; f
SAMPLE
= f
SAMPLE
MAX
6
SCLK Off
SCLK On
V
DD
= 5 V; f
SAMPLE
= f
SAMPLE
MAX
6
V
DD
= 3 V; f
SAMPLE
= f
SAMPLE
MAX
6
V
DD
= 5 V; SCLK Off
V
DD
= 3 V; SCLK Off
NOTES
1
Temperature ranges as follows: A, B Versions: –40∞C to +85∞; S Version: –55∞C to +125∞C.
2
Operational from V
DD
= 2.0 V.
3
See Terminology section.
4
Maximum B, S version specifications apply as typical figures when V
DD
= 5.25 V.
Sample tested at 25∞C to ensure compliance.
A Version: f
SAMPLE
MAX = 1 MSPS; B, S Versions: f
SAMPLE
MAX = 600 kSPS.
7
See Power vs. Throughput Rate section.
Specifications subject to change without notice.
–2–
REV. C
AD7477–SPECIFICATIONS
1
(V
Parameter
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
, SCLK Pin
Input Current, I
IN
,
CS
Pin
Input Capacitance, C
IN3, 4
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
3, 4
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
V
DD
I
DD
Normal Mode (Static)
Normal Mode (Operational)
Full Power-Down Mode
Power Dissipation
5
Normal Mode (Operational)
Full Power-Down
61
–73
–74
–78
–78
10
30
6.5
10
±
1
±
0.9
±
1
±
1
DD
= 2.7 V to 5.25 V, f
SCLK
= 20 MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
A Version
1, 2
S Version
1, 2
61
–73
–74
–78
–78
10
30
6.5
10
±
1
±
0.9
±
1
±
1
0 to V
DD
±
1
30
2.4
0.8
0.4
±
1
±
1
10
Unit
dB min
dB max
dB max
dB typ
dB typ
ns typ
ps typ
MHz typ
Bits
LSB max
LSB max
LSB max
LSB max
V
mA
max
pF typ
V min
V max
V max
mA
max
mA
typ
pF max
V min
V max
mA
max
pF max
Test Conditions/Comments
f
IN
= 100 kHz Sine Wave, f
SAMPLE
= 1 MSPS
fa = 103.5 kHz, fb = 113.5 kHz
fa = 103.5 kHz, fb = 113.5 kHz
@ 3 dB
Guaranteed No Missed Codes to 10 Bits
0 to V
DD
±
1
30
2.4
0.8
0.4
±
1
±
1
10
V
DD
= 5 V
V
DD
= 3 V
Typically 10 nA, V
IN
= 0 V or V
DD
V
DD
– 0.2
V
DD
– 0.2
0.4
0.4
±
10
±
10
10
10
Straight (Natural) Binary
800
400
1
2.7/5.25
2
1
3.5
1.6
1
80
17.5
4.8
5
800
400
1
2.7/5.25
2
1
3.5
1.6
1
80
17.5
4.8
5
I
SOURCE
= 200
mA;
V
DD
= 2.7 V to 5.25 V
I
SINK
= 200
mA
ns max
ns max
MSPS max
V min/max
mA typ
mA typ
mA max
mA max
mA
max
mA
max
mW max
mW max
mW
max
16 SCLK Cycles with SCLK at 20 MHz
See Serial Interface Section
Digital I/Ps = 0 V or V
DD
V
DD
= 4.75 V to 5.25 V; SCLK On or Off
V
DD
= 2.7 V to 3.6 V; SCLK On or Off
V
DD
= 4.75 V to 5.25 V; f
SAMPLE
= 1 MSPS
V
DD
= 2.7 V to 3.6 V; f
SAMPLE
= 1 MSPS
SCLK Off
SCLK On
V
DD
= 5 V; f
SAMPLE
= 1 MSPS
V
DD
= 3 V; f
SAMPLE
= 1 MSPS
V
DD
= 5 V; SCLK Off
NOTES
1
Temperature ranges as follows: A Version: –40∞C to +85∞C; S Version: –55∞C to +125∞C.
2
Operational from V
DD
= 2.0 V, with input high voltage, V
INH
= 1.8 V min.
3
See Terminology section.
4
Sample tested at 25∞C to ensure compliance.
5
See Power vs. Throughput Rate section.
Specifications subject to change without notice.
REV. C
–3–
AD7476–SPECIFICATIONS
1
(V
8
Parameter
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Total Unadjusted Error (TUE)
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
, SCLK Pin
Input Current, I
IN
,
CS
Pin
Input Capacitance, C
IN3, 4
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
3, 4
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
V
DD
I
DD
Normal Mode (Static)
Normal Mode (Operational)
Full Power-Down Mode
Power Dissipation
5
Normal Mode (Operational)
Full Power-Down
49
–65
–65
–68
–68
10
30
6.5
8
±
0.5
±
0.5
±
0.5
±
0.5
±
0.5
DD
= 2.7 V to 5.25 V, f
SCLK
= 20 MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
A Version
1, 2
S Version
1, 2
49
–65
–65
–68
–68
10
30
6.5
8
±
0.5
±
0.5
±
0.5
±
0.5
±
0.5
0 to V
DD
±
1
30
2.4
0.8
0.4
±
1
±
1
10
Unit
dB min
dB max
dB max
dB typ
dB typ
ns typ
ps typ
MHz typ
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
V
mA
max
pF typ
V min
V max
V max
mA
max
mA
typ
pF max
V min
V max
mA
max
pF max
Test Conditions/Comments
f
IN
= 100 kHz Sine Wave, f
SAMPLE
= 1 MSPS
fa = 498.7 kHz, fb = 508.7 kHz
fa = 498.7 kHz, fb = 508.7 kHz
@ 3 dB
Guaranteed No Missed Codes to Eight Bits
0 to V
DD
±
1
30
2.4
0.8
0.4
±
1
±
1
10
V
DD
= 5 V
V
DD
= 3 V
Typically 10 nA, V
IN
= 0 V or V
DD
V
DD
– 0.2
V
DD
– 0.2
0.4
0.4
±
10
±
10
10
10
Straight (Natural) Binary
800
400
1
2.7/5.25
2
1
3.5
1.6
1
80
17.5
4.8
5
800
400
1
2.7/5.25
2
1
3.5
1.6
1
80
17.5
4.8
5
I
SOURCE
= 200
mA;
V
DD
= 2.7 V to 5.25 V
I
SINK
= 200
mA
ns max
ns max
MSPS max
V min/max
mA typ
mA typ
mA max
mA max
mA
max
mA
max
mW max
mW max
mW
max
16 SCLK Cycles with SCLK at 20 MHz
See Serial Interface Section
Digital I/Ps = 0 V or V
DD
V
DD
= 4.75 V to 5.25 V; SCLK On or Off
V
DD
= 2.7 V to 3.6 V; SCLK On or Off
V
DD
= 4.75 V to 5.25 V; f
SAMPLE
= 1 MSPS
V
DD
= 2.7 V to 3.6 V; f
SAMPLE
= 1 MSPS
SCLK Off
SCLK On
V
DD
= 5 V; f
SAMPLE
= 1 MSPS
V
DD
= 3 V; f
SAMPLE
= 1 MSPS
V
DD
= 5 V; SCLK Off
NOTES
1
Temperature ranges as follows: A Version: –40∞C to +85∞C; S Version: –55∞C to +125∞C.
2
Operational from V
DD
= 2.0 V, with input high voltage, V
INH
= 1.8 V min.
3
See Terminology section.
4
Sample tested at 25∞C to ensure compliance.
5
See Power vs. Throughput Rate section.
Specifications subject to change without notice.
–4–
REV. C
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EEWORLD
