AT32UC3A0512 datasheet, PDF - EEWORLD Datasheet

Features

•

High Performance, Low Power AVR

®

32 UC 32-Bit Microcontroller

– Compact Single-cycle RISC Instruction Set Including DSP Instruction Set

– Read-Modify-Write Instructions and Atomic Bit Manipulation

– Performing 1.49 DMIPS / MHz

Up to 91 DMIPS Running at 66 MHz from Flash (1 Wait-State)

Up to 49 DMIPS Running at 33MHz from Flash (0 Wait-State)

– Memory Protection Unit

Multi-hierarchy Bus System

– High-Performance Data Transfers on Separate Buses for Increased Performance

– 15 Peripheral DMA Channels Improves Speed for Peripheral Communication

Internal High-Speed Flash

– 512K Bytes, 256K Bytes, 128K Bytes Versions

– Single Cycle Access up to 33 MHz

– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed

– 4ms Page Programming Time and 8ms Full-Chip Erase Time

– 100,000 Write Cycles, 15-year Data Retention Capability

– Flash Security Locks and User Defined Configuration Area

Internal High-Speed SRAM, Single-Cycle Access at Full Speed

– 64K Bytes (512KB and 256KB Flash), 32K Bytes (128KB Flash)

External Memory Interface on AT32UC3A0 Derivatives

– SDRAM / SRAM Compatible Memory Bus (16-bit Data and 24-bit Address Buses)

Interrupt Controller

– Autovectored Low Latency Interrupt Service with Programmable Priority

System Functions

– Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator

– Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL) allowing

Independant CPU Frequency from USB Frequency

– Watchdog Timer, Real-Time Clock Timer

Universal Serial Bus (USB)

– Device 2.0 Full Speed and On-The-Go (OTG) Low Speed and Full Speed

– Flexible End-Point Configuration and Management with Dedicated DMA Channels

– On-chip Transceivers Including Pull-Ups

Ethernet MAC 10/100 Mbps interface

– 802.3 Ethernet Media Access Controller

– Supports Media Independent Interface (MII) and Reduced MII (RMII)

One Three-Channel 16-bit Timer/Counter (TC)

– Three External Clock Inputs, PWM, Capture and Various Counting Capabilities

One 7-Channel 16-bit Pulse Width Modulation Controller (PWM)

Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)

– Independant Baudrate Generator, Support for SPI, IrDA and ISO7816 interfaces

– Support for Hardware Handshaking, RS485 Interfaces and Modem Line

Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals

One Synchronous Serial Protocol Controller

– Supports I2S and Generic Frame-Based Protocols

One Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible

One 8-channel 10-bit Analog-To-Digital Converter

16-bit Stereo Audio Bitstream

– Sample Rate Up to 50 KHz

•

AVR

®

32

32-Bit

Microcontroller

AT32UC3A0512

AT32UC3A0256

AT32UC3A0128

AT32UC3A1512

AT32UC3A1256

AT32UC3A1128

Preliminary

Summary

•

32058FS–AVR32–08/08

AT32UC3A

•

On-Chip Debug System (JTAG interface)

– Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace

•

100-pin TQFP (69 GPIO pins), 144-pin LQFP (109 GPIO pins)

•

5V Input Tolerant I/Os

•

Single 3.3V Power Supply or Dual 1.8V-3.3V Power Supply

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32058FS–AVR32–08/08

AT32UC3A

1. Description

The AT32UC3A is a complete System-On-Chip microcontroller based on the AVR32 UC RISC

processor running at frequencies up to 66 MHz. AVR32 UC is a high-performance 32-bit RISC

microprocessor core, designed for cost-sensitive embedded applications, with particular empha-

sis on low power consumption, high code density and high performance.

The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt con-

troller for supporting modern operating systems and real-time operating systems. Higher

computation capabilities are achievable using a rich set of DSP instructions.

The AT32UC3A incorporates on-chip Flash and SRAM memories for secure and fast access.

For applications requiring additional memory, an external memory interface is provided on

AT32UC3A0 derivatives.

The Peripheral Direct Memory Access controller (PDCA) enables data transfers between periph-

erals and memories without processor involvement. PDCA drastically reduces processing

overhead when transferring continuous and large data streams between modules within the

MCU.

The PowerManager improves design flexibility and security: the on-chip Brown-Out Detector

monitors the power supply, the CPU runs from the on-chip RC oscillator or from one of external

oscillator sources, a Real-Time Clock and its associated timer keeps track of the time.

The Timer/Counter includes three identical 16-bit timer/counter channels. Each channel can be

independently programmed to perform frequency measurement, event counting, interval mea-

surement, pulse generation, delay timing and pulse width modulation.

The PWM modules provides seven independent channels with many configuration options

including polarity, edge alignment and waveform non overlap control. One PWM channel can

trigger ADC conversions for more accurate close loop control implementations.

The AT32UC3A also features many communication interfaces for communication intensive

applications. In addition to standard serial interfaces like UART, SPI or TWI, other interfaces like

flexible Synchronous Serial Controller, USB and Ethernet MAC are available.

The Synchronous Serial Controller provides easy access to serial communication protocols and

audio standards like I2S.

The Full-Speed USB 2.0 Device interface supports several USB Classes at the same time

thanks to the rich End-Point configuration. The On-The-GO (OTG) Host interface allows device

like a USB Flash disk or a USB printer to be directly connected to the processor.

The media-independent interface (MII) and reduced MII (RMII) 10/100 Ethernet MAC module

provides on-chip solutions for network-connected devices.

AT32UC3A integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive

real-time trace, full-speed read/write memory access in addition to basic runtime control.

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32058FS–AVR32–08/08

AT32UC3A

2. Configuration Summary

The table below lists all AT32UC3A memory and package configurations:

Device

AT32UC3A0512

AT32UC3A0256

AT32UC3A0128

AT32UC3A1512

AT32UC3A1256

AT32UC3A1128

Flash

512 Kbytes

256 Kbytes

128 Kbytes

512 Kbytes

256 Kbytes

128 Kbytes

SRAM

64 Kbytes

32 Kbytes

64 Kbytes

32 Kbytes

Ext. Bus Interface

yes

no

Ethernet

MAC

yes

Package

144 lead LQFP

100 lead TQFP

3. Abbreviations

• GCLK: Power Manager Generic Clock

• GPIO: General Purpose Input/Output

• HSB: High Speed Bus

• MPU: Memory Protection Unit

• OCD: On Chip Debug

• PB: Peripheral Bus

• PDCA: Peripheral Direct Memory Access Controller (PDC) version A

• USBB: USB On-The-GO Controller version B

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32058FS–AVR32–08/08

AT32UC3A

4. Blockdiagram

Figure 4-1.

Blockdiagram

TC K

TD O

TD I

TM S

M C KO

M D O [5..0]

M SEO [1..0]

EVTI_N

EVTO _N

VBU S

D+

D-

ID

VBOF

NEXUS

CLASS 2+

OCD

UC CPU

M EM O R Y PR O TEC TIO N U N IT

MEMORY INTERFACE

JTAG

INTERFACE

LOC AL BU S

IN TER FAC E

FAST G PIO

INSTR

INTERFACE

PBB

DATA

INTERFAC E

64 KB

SR AM

FLASH

CONTROLLER

USB

INTERFACE

DM A

S

M

S

512 KB

FLASH

S

ETHERNET

M AC

PB

GENERAL PURPOSE IOs

MDC,

TXD [3..0],

TX _C LK,

TX_EN ,

TX_ER ,

SPEED

M D IO

S

C O N FIG U R ATIO N

HS

B

S

R EG ISTERS BU S

M

EXTERNAL BUS INTERFACE

(SDRAM & STATIC MEMORY

CONTROLLER)

C O L,

C R S,

R XD [3..0],

R X_C LK,

R X_D V,

RX_ER

DM A

HIG H SPEED

BUS M ATRIX

D ATA[15..0]

ADD R [23..0]

N C S[3..0]

NRD

N W AIT

N W E0

N W E1

N W E3

R AS

C AS

SD A10

SD C K

SD C KE

SD C S 0

SD W E

H SB

HSB-PB

BRIDG E B

HSB-PB

BRIDG E A

PB

PBA

PERIPHER AL

DM A

C ON TR O LLER

INTERR UPT

CO NTRO LLER

EXTIN T[7..0]

KPS[7..0]

N M I_N

EXTERNAL

INTERRUPT

C O NTRO LLER

USART1

GENERAL PURPOSE IOs

PA

PB

PC

PX

R XD

TXD

CLK

R TS, C TS

D SR , D TR, D C D, R I

R XD

TXD

CLK

R TS, C TS

PDC

PA

PB

PC

PX

R EAL TIM E

C O UNTER

USART0

USART2

USART3

PDC

W ATC HDO G

TIM ER

115 kHz

RC O SC

XIN 32

XOU T32

XIN 0

XOU T0

XIN 1

XOU T1

SERIAL

PER IPHERAL

INTERFACE 0/1

SYN CHRO NO US

SERIAL

CO NTRO LLER

SC K

M ISO , M OSI

N PC S0

N PC S[3..1]

TX_CLO CK, TX _FRAM E_SYNC

TX_DATA

RX_CLO CK, RX_FRAM E_SYNC

RX_DATA

PO W ER

M ANAG ER

CLO C K

G ENERATO R

CLO C K

CO NTRO LLER

SLEEP

CO NTRO LLER

RESET

CO NTRO LLER

32 KHz

O SC

O SC 0

O SC 1

PLL0

PLL1

PDC

TW O -W IRE

INTERFACE

PDC

SC L

SD A

PULSE W IDTH

M O DULATIO N

CO NTRO LLER

ANALO G TO

DIG ITAL

CO NVERTER

AUDIO

BITSTR EAM

DAC

PDC

PW M [6..0]

PDC

RESET_N

GC LK [3..0]

AD [7..0]

AD VR EF

PDC

A[2..0]

B[2..0]

C LK[2..0]

TIM ER /CO UN TER

D ATA[1..0]

D ATAN [1..0]

5

32058FS–AVR32–08/08

AT32UC3A0512

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