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HD74LV161AFP

Description
LV/LV-A/LVX/H SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, FP-16DAV
Categorylogic    logic   
File Size107KB,16 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
Environmental Compliance  
Download Datasheet Parametric View All

HD74LV161AFP Overview

LV/LV-A/LVX/H SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, FP-16DAV

HD74LV161AFP Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Parts packaging codeSOIC
package instructionSOP,
Contacts16
Reach Compliance Codecompliant
Counting directionUP
seriesLV/LV-A/LVX/H
JESD-30 codeR-PDSO-G16
length10.06 mm
Load/preset inputYES
Logic integrated circuit typeBINARY COUNTER
Operating modeSYNCHRONOUS
Humidity sensitivity level1
Number of digits4
Number of functions1
Number of terminals16
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)22.5 ns
Certification statusNot Qualified
Maximum seat height2.2 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width5.5 mm
minfmax115 MHz
Base Number Matches1
HD74LV161A
Synchronous 4-bit Binary Counter (Direct Clear)
REJ03D0319–0400Z
(Previous ADE-205-264B (Z))
Rev.4.00
Jun. 04, 2004
Description
The HD74LV161A is 4-bit binary counters. All flip flops are clocked simultaneously on the low to high to transition
(positive edge) of the clock input waveform. These counters may be preset using the load input. Presetting of all four
flip flops is synchronous to the rising edge of clock. When load is held low counting is disabled and the data on the A,
B, C and D inputs is loaded into the counter on the rising edge clock. If the load input is taken high before the positive
edge of clock, the count operation will be unaffected.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the
low-power consumption extends the battery life.
Features
V
CC
= 2.0 V to 5.5 V operation
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25°C)
Typical V
OH
undershoot > 2.3 V (@V
CC
= 3.3 V, Ta = 25°C)
Output current ±6 mA (@V
CC
= 3.0 V to 3.6 V), ±12 mA (@V
CC
= 4.5 V to 5.5 V)
Ordering Information
Package Type
SOP–16 pin(JEITA)
SOP–16 pin(JEDEC)
TSSOP–16 pin
Package Code
FP–16DAV
FP–16DNV
TTP–16DAV
Package
Abbreviation
FP
RP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
Part Name
HD74LV161AFPEL
HD74LV161ARPEL
HD74LV161ATELL
Note: Please consult the sales office for the above package availability.
Rev.4.00 Jun. 04, 2004 page 1 of 15
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