Features
•
EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1- and
2,097,152 x 1-bit Serial Memories Designed to Store Configuration Programs for
Altera
®
FLEX
®
and APEX
™
FPGAs (Device Selection Guide Included)
Available as a 3.3V (±10%) and 5.0V (±5% Commercial, ±10% Industrial) Version
In-System Programmable (ISP) via 2-wire Bus
Simple Interface to SRAM FPGAs
Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera FLEX, APEX
Devices, ORCA
®
FPGAs, Xilinx
®
XC3000, XC4000, XC5200, Spartan
®
, Virtex
™
FPGAs,
Motorola MPA1000 FPGAs
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
Very Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available 8-lead PDIP, 20-lead PLCC and 32-lead TQFP Packages (Pin Compatible
Across Product Family)
Emulation of Atmel’s AT24CXXX Serial EEPROMs
Low-power Standby Mode
High-reliability
– Endurance: 100,000 Write Cycles
– Data Retention: 90 Years for Industrial Parts (at 85°C) and 190 Years for
Commercial Parts (at 70°C)
Green (Pb/Halide-free/RoHS Compliant) Package Options Available
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FPGA
Configuration
EEPROM
Memory
AT17LV65A
AT17LV128A
AT17LV256A
AT17LV512A
AT17LV010A
AT17LV002A
3.3V and 5V
System Support
•
1. Description
The AT17A series FPGA configuration EEPROMs (Configurators) provide an easy-to-
use, cost-effective configuration memory for Field Programmable Gate Arrays. The
AT17A series device is packaged in the 8-lead PDIP
(1)
, 20-lead PLCC and 32-lead
TQFP, see
Table 1-1.
The AT17A series configurator uses a simple serial-access pro-
cedure to configure one or more FPGA devices. The user can select the polarity of the
reset function by programming four EEPROM bytes.These devices also support a
write-protection mechanism within its programming mode.
Note:
1. The 8-lead LAP, PDIP and SOIC packages for the AT17LV65A/128A/256A do not
have an A label. However, the 8-lead packages are pin compatible with the 8-lead
package of Altera’s EEPROMs, refer to the AT17LV65/128/256/512/010/002/040
datasheet available on the Atmel web site for more information.
The AT17A series configurators can be programmed with industry-standard program-
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
Table 1-1.
AT17A Series Packages
AT17LV65A/
AT17LV128A/
AT17LV256A
Yes
Yes
–
Package
8-lead
PDIP
20-lead
PLCC
32-lead
TQFP
AT17LV512A
Yes
Yes
–
AT17LV010A
Yes
Yes
Yes
AT17LV002A
–
Yes
Yes
2322G–CNFG–03/06
2. Pin Configuration
Figure 2-1.
8-lead PDIP
DATA
DCLK
(1)
(WP ) RESET/OE
nCS
1
2
3
4
8
7
6
5
VCC
SER_EN
(A2) nCASC
(4)
GND
Figure 2-2.
20-lead PLCC
NC
DATA
NC
VCC
NC
3
2
1
20
19
nCS
GND
NC
(A2) nCASC
(4)
NC
9
10
11
12
13
DCLK
(2)
WP1
NC
NC
(1)
(WP ) RESET/OE
4
5
6
7
8
18
17
16
15
14
SER_EN
NC
NC
NC
(READY
(2)
)
NC
Figure 2-3.
32-lead TQFP
NC
DATA
NC
NC
NC
VCC
NC
NC
32
31
30
29
28
27
26
25
NC
DCLK
NC
(3)
(WP1 ) NC
NC
NC
RESET/OE
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
NC
SER_EN
NC
NC
READY
NC
NC
NC
Notes:
1. This pin is only available on AT17LV65A/128A/256A devices.
2. This pin is only available on AT17LV512A/010A/002A devices.
3. This pin is only available on AT17LV010A/002A devices.
4. The nCASC feature is not available on the AT17LV65A device.
2
AT17LV65A/128A/256A/512A/002A
2322G–CNFG–03/06
NC
nCS
NC
GND
NC
NC
(A2) nCASC
NC
AT17LV65A/128A/256A/512A/002A
Figure 2-4.
Block Diagram
SER_EN
WP1
(2)
OSCILLATOR
CONTROLL
OSCILLATOR
(3)
POWER ON
RESET
DCLK
READY
(2)
RESET/OE
(1)
(WP )
nCS
nCASC
Notes:
1. This pin is only available on AT17LV65A/128A/256A devices.
2. This pin is only available on AT17LV512A/010A/002A devices.
3. The nCASC feature is not available on the AT17LV65A device.
3
2322G–CNFG–03/06
3. Device Description
The control signals for the configuration EEPROM (nCS, RESET/OE and DCLK) interface
directly with the FPGA device control signals. All FPGA devices can control the entire configura-
tion process and retrieve data from the configuration EEPROM without requiring an external
controller.
The configuration EEPROM’s RESET/OE and nCS pins control the tri-state buffer on the DATA
output pin and enable the address counter and the oscillator. When RESET/OE is driven Low,
the configuration EEPROM resets its address counter and tri-states its DATA pin. The nCS pin
also controls the output of the AT17A series configurator. If nCS is held High after the
RESET/OE pulse, the counter is disabled and the DATA output pin is tri-stated. When nCS is
driven subsequently Low, the counter and the DATA output pin are enabled. When RESET/OE
is driven Low again, the address counter is reset and the DATA output pin is tri-stated, regard-
less of the state of the nCS.
When the configurator has driven out all of its data and nCASC is driven Low, the device tri-
states the DATA pin to avoid contention with other configurators. Upon power-up, the address
counter is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High,
this document will describe RESET/OE.
4. Pin Description
AT17LV65A/
AT17LV128A/
AT17LV256A
Name
DATA
DCLK
WP1
I/O
I/O
I
I
I
I
20
PLCC
2
4
–
8
9
10
O
12
A2
READY
SER_EN
V
CC
Note:
I
O
I
–
18
20
–
7
8
15
18
20
20
23
27
15
18
20
20
23
27
6
12
15
12
15
8
PDIP
1
2
–
3
4
5
AT17LV512A/
AT17LV010A
20
PLCC
2
4
5
8
9
10
32
TQFP
31
2
4
7
10
12
AT17LV002A
20
PLCC
2
4
5
8
9
10
32
TQFP
31
2
4
7
10
12
RESET/
OE
nCS
GND
nCASC
1. The nCASC feature is not available on the AT17LV65A device.
4
AT17LV65A/128A/256A/512A/002A
2322G–CNFG–03/06
AT17LV65A/128A/256A/512A/002A
4.1
DATA
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
4.2
DCLK
Clock output or clock input. Rising edges on DCLK increment the internal address counter and
present the next bit of data to the DATA pin. The counter is incremented only if the RESET/OE
input is held High, the nCS input is held Low, and all configuration data has not been transferred
to the target device (otherwise, as the master device, the DCLK pin drives Low).
4.3
WP1
WRITE PROTECT (1). This pin is used to protect portions of memory during programming, and
it is disabled by default due to internal pull-down resistor. This input pin is not used during FPGA
loading operations. This pin is only available on AT17LV512A/010A/002A devices.
4.4
RESET/OE
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low logic level
resets the address counter. A High logic level (with nCS Low) enables DATA and permits the
address counter to count. In the mode, if this pin is Low (reset), the internal oscillator becomes
inactive and DCLK drives Low. The logic polarity of this input is programmable and must be pro-
grammed active High (RESET active Low) by the user during programming for Altera
applications.
4.5
WP
Write protect (WP) input (when nCS is Low) during programming only (SER_EN Low). When
WP is Low, the entire memory can be written. When WP is enabled (High), the lowest block of
the memory cannot be written. This pin is only available on AT17LV65A/128A/256A devices.
4.6
nCS
Chip Select input (active Low). A Low input (with OE High) allows DCLK to increment the
address counter and enables DATA to drive out. If the AT17A series is reset with nCS Low, the
device initializes as the first (and master) device in a daisy-chain. If the AT17A series is reset
with nCS High, the device initializes as a subsequent AT17A series device in the chain.
4.7
GND
Ground pin. A 0.2 µF decoupling capacitor between V
CC
and GND is recommended.
4.8
nCASC
Cascade Select Output (active Low). This output goes Low when the address counter has
reached its maximum value. In a daisy-chain of AT17A series devices, the nCASC pin of one
device is usually connected to the nCS input pin of the next device in the chain, which permits
DCLK from the master configurator to clock data from a subsequent AT17A series device in the
chain. This feature is not available on the AT17LV65A device.
4.9
A2
Device selection input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
5
2322G–CNFG–03/06
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