64Kx4 Bit (with OE) High Speed Static RAM(5V Operating).
CMOS SRAM
Revision History
Rev No.
Rev. 0.0
Rev. 1.0
History
Initial release with Preliminary.
Release to Final Data Sheet.
Draft Data
Aug. 1. 1998
Nov. 2. 1998
Remark
Preliminary
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev1.0
November 1998
KM64258E
64K x 4 Bit High-Speed CMOS Static RAM
FEATURES
• Fast Access Time 10,12,15ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 20mA(Max.)
(CMOS) : 2mA(Max.)
Operating KM64258E - 10 : 70mA(Max.)
KM64258E - 12 : 70mA(Max.)
KM64258E - 15 : 70mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible With 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Standard Pin Configuration
KM64258EJ : 28-SOJ-300
CMOS SRAM
GENERAL DESCRIPTION
The KM64258E is a 262,144-bit high-speed Static Random
Access Memory organized as 65,536 words by 4 bits. The
KM64258E uses 4 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The KM64258E is packaged in
a 300 mil 28-pin plastic SOJ .
PIN CONFIGURATION
(Top View)
N.C
A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 Vcc
27 A
15
26 A
14
25 A
13
24 A
12
23 A
11
FUNCTIONAL BLOCK DIAGRAM
A
1
A
2
A
3
Clk Gen.
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
Pre-Charge-Circuit
A
4
A
5
A
6
A
7
SOJ
22 A
10
21 N.C.
20 N.C.
19 I/O
4
18 I/O
3
17 I/O
2
16 I/O
1
15 WE
Row Select
Memory Array
512 Rows
128x4 Columns
A
8
A
9
CS
OE
V
SS
I/O
1
~I/O
4
Data
Cont.
CLK
Gen.
A
9
I/O Circuit
Column Select
PIN FUNCTION
A
10
A
11
A
12
A
13
A
14
A
15
Pin Name
A
0
- A
15
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power(+5.0V)
Ground
No Connection
CS
WE
OE
WE
CS
OE
I/O
1
~ I/O
4
V
CC
V
SS
N.C
Rev1.0
November 1998
KM64258E
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Symbol
V
IN
, V
OUT
V
CC
P
D
T
STG
T
A
Rating
-0.5 to 7.0
-0.5 to 7.0
1.0
-65 to 150
0 to 70
CMOS SRAM
Unit
V
V
W
°C
°C
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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