ACS8525A LC/P
Line Card Protection Switch for SONET/SDH Systems
ADVANCED COMMS & SENSING
COMMUNICATIONS
Description
FINAL
Features
DATASHEET
The ACS8525A is a highly integrated, single-chip solution
for “Hit-less” protection switching of SEC (SDH/SONET
Equipment Clock) + Sync clock “Groups”, from Master
and Slave SETS clock cards and a third (Stand-by) source,
for Line Cards in a SONET or SDH Network Element. The
ACS8525A has fast activity monitors on the SEC clock
inputs and will implement automatic system protection
switching against the Master clock failure. The selection
of the Master/Slave input can be forced by a Force Fast
Switch pin. If both the Master and Slave input clocks fail,
the Stand-by “Group” is selected or, if no Stand-by is
available, the device enters Digital Holdover mode.
The ACS8525A can perform frequency translation,
converting, for example, an 8 kHz SEC input clock from a
backplane into a 155.52 MHz clock for local line cards.
Master and Slave SEC inputs to the device support
TTL/CMOS and PECL/LVDS. The Stand-by SEC and three
Sync inputs are TTL/CMOS only.
The ACS8525A generates two SEC clock outputs, via one
PECL/LVDS and one TTL/CMOS port, with spot
frequencies from 2 kHz up to 311.04 MHz (up to 155.52
MHz on the TTL/CMOS port). It also provides an 8 kHz
Frame Sync and a 2 kHz Multi-Frame Sync signal output
with programmable pulse width and polarity.
The ACS8525 includes a Serial Port, which can be SPI
compatible, providing access to the configuration and
status registers for device setup.
IEEE 1149.1 JTAG Boundary Scan is supported.
Block Diagram
Figure 1 Block Diagram of the ACS8525A LC/P
3 x SEC/Sync Input Groups
SEC1 & SEC2:
TTL/PECL/LVDS,
SEC3 and all Syncs
TTL only
SEC1
Master
SYNC1
SEC2
Slave
SYNC2
SEC3
Stand-by
SYNC3
SEC Inputs:
Programmable
Frequencies
2 kHz, 4 kHz,
TCK
N x 8 kHz
TDI
1.544/2.048 MHz
TMS
6.48 MHz
TRST
19.44 MHz
TDO
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
SONET/SDH applications up to OC-3/STM-1 bit rate.
Switches between grouped inputs (SEC/Sync pairs).
Inputs: three SECs at any of 2, 4, 8 kHz (and N x 8 kHz
multiples up to 155.52 MHz), plus Frame Sync/Multi-
Frame Sync.
Outputs: two SEC clocks at any of several spot
frequencies from 2 kHz up to 77.76 MHz via the
TTL/CMOS port and up to 311.04 MHz via the
PECL/LVDS port.
Selectable clock I/O port technologies.
Modes for E3/DS3 and multiple E1/DS1 rate output
clocks.
Frequency translation of SEC input clock to a different
local line card clock.
Robust input clock source activity monitoring on all
inputs.
Supports Free-run, Locked and Digital Holdover
modes of operation.
Automatic “Hit-less” source switchover on loss of
input.
External force fast switch between SEC1/SEC2 inputs.
Phase Build-out for output clock phase continuity
during input switchover.
PLL “Locked” and “Acquisition” bandwidths
individually selectable from 18, 35 or 70 Hz.
Serial interface for device set-up.
Single 3.3 V operation.
Operating temperature (ambient) of 0 to +70°C.
Available in LQFP 64 package.
Lead (Pb)-free version available (ACS8525T), RoHS
and WEEE compliant.
DPLL1
Input
SEC Port
Monitors
and
Input
Selection
Control
DPLL2
MUX
2
APLL2
Output
Port
Frequency
Selection
MUX
1
APLL 1
SEC Outputs:
01 (PECL/LVDS)
02 (TTL)
Selector
Digital Feedback
E1/DS1
Synthesis
APLL3
Sync Outputs:
MFrSync 2 kHz (TTL)
FrSync 8 kHz (TTL)
01 and 02:
E1/DS1 (2.048/1.544 MHz)
and frequency multiples:
1.5x, 2x, 3x, 4x, 6x, 12x,
16x, and 24x E1/DS1
E3/DS3, 2 kHz, 8 kHz.
and OC-N* rates: OC-1 51.84 MHz
OC-3 155.52 MHz and derivatives:
6.48 MHz (O2 port only)
19.44 MHz, 25.92 MHz,
38.88 MHz, 51.84 MHz, 77.76 MHz,
155.52 MHz (01 port only)
311.04 MHz (01 port only)
F8525D_001BLOCKDIA_05
IEEE
1149.1
JTAG
Chip
Clock
Generator
Priority Register Set
Table
Serial Interface
Port
TCXO or
XO
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ACS8525A LC/P
ADVANCED COMMS & SENSING
Table of Contents
FINAL
DATASHEET
Section
Page
Description ................................................................................................................................................................................................. 1
Block Diagram ............................................................................................................................................................................................1
Features .....................................................................................................................................................................................................1
Pin Diagram ...............................................................................................................................................................................................4
Pin Description ...........................................................................................................................................................................................5
Introduction ................................................................................................................................................................................................6
General Description ...................................................................................................................................................................................7
Inputs .................................................................................................................................................................................................7
Preconfiguring Inputs ...............................................................................................................................................................8
PECL/LVDS Input Port Selection .............................................................................................................................................9
Input Locking Frequency Modes .............................................................................................................................................9
Input SEC Activity Monitors ..............................................................................................................................................................9
Leaky Bucket Accumulator ................................................................................................................................................... 10
Fast Activity Monitor .............................................................................................................................................................. 11
Selector ........................................................................................................................................................................................... 11
Selection of Input SECs ......................................................................................................................................................... 11
External Protection Switching Mode-SRCSW pin ................................................................................................................ 13
Output Clock Phase Continuity on Source Switchover ....................................................................................................... 13
Forcing of the Operating Mode of the Device ...................................................................................................................... 13
Phase Locked Loops (PLLs) .......................................................................................................................................................... 13
PLL Overview ......................................................................................................................................................................... 13
PLL Architecture .................................................................................................................................................................... 14
PLL Operational Controls ...................................................................................................................................................... 17
Phase Compensation Functions .......................................................................................................................................... 19
DPLL Feature Summary ........................................................................................................................................................ 20
Outputs ........................................................................................................................................................................................... 22
PECL/LVDS Output Port Selection ....................................................................................................................................... 22
Output Frequency Selection and PLL Configuration ........................................................................................................... 22
Operating Modes (States) of the Device ...................................................................................................................................... 30
Free-run Mode ....................................................................................................................................................................... 30
Pre-locked Mode ................................................................................................................................................................... 30
Locked Mode ......................................................................................................................................................................... 30
Lost-phase Mode ................................................................................................................................................................... 30
Digital Holdover Mode ........................................................................................................................................................... 30
Pre-locked2 Mode ................................................................................................................................................................. 32
Local Oscillator Clock ..................................................................................................................................................................... 32
Status Reporting and Phase Measurement ................................................................................................................................. 32
Input Status Interrupts .......................................................................................................................................................... 32
Input Status Information ....................................................................................................................................................... 32
DPLL Frequency Reporting ................................................................................................................................................... 32
Measuring Phase Between Master and Slave/Stand-by SEC Sources ............................................................................. 33
Sync Reference Sources ............................................................................................................................................................... 33
Aligning Phase of MFrSync and FrSync Outputs to Phase of Sync Inputs ......................................................................... 34
Power-On Reset .............................................................................................................................................................................. 35
Serial Interface ............................................................................................................................................................................... 35
Register Map ........................................................................................................................................................................................... 38
Register Organization .................................................................................................................................................................... 38
Multi-word Registers ............................................................................................................................................................. 38
Register Access ..................................................................................................................................................................... 38
Interrupt Enable and Clear ................................................................................................................................................... 38
Defaults .................................................................................................................................................................................. 38
Register Descriptions ............................................................................................................................................................................. 42
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ACS8525A LC/P
ADVANCED COMMS & SENSING
FINAL
DATASHEET
Section
Page
Electrical Specifications ......................................................................................................................................................................... 98
JTAG ................................................................................................................................................................................................ 98
Over-voltage Protection ................................................................................................................................................................. 98
ESD Protection ............................................................................................................................................................................... 98
Latchup Protection ......................................................................................................................................................................... 98
Maximum Ratings .......................................................................................................................................................................... 99
Operating Conditions ..................................................................................................................................................................... 99
DC Characteristics ......................................................................................................................................................................... 99
Jitter Performance ....................................................................................................................................................................... 103
Input/Output Timing .................................................................................................................................................................... 105
Package Information ............................................................................................................................................................................ 106
Thermal Conditions ...................................................................................................................................................................... 107
Application Information ........................................................................................................................................................................ 108
References ............................................................................................................................................................................................ 109
Abbreviations ........................................................................................................................................................................................ 109
Notes ..................................................................................................................................................................................................... 110
Trademark Acknowledgements ........................................................................................................................................................... 110
Revision Status/History ....................................................................................................................................................................... 111
Ordering Information ............................................................................................................................................................................ 112
Disclaimers ................................................................................................................................................................................... 112
Contacts ................................................................................................................................................................................................ 112
Revision 1.00/September 2007 © Semtech Corp.
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ACS8525A LC/P
ADVANCED COMMS & SENSING
Pin Diagram
FINAL
DATASHEET
Figure 2 ACS8525A Pin Diagram Line Card Protection Switch for SONET/SDH Systems
Revision 1.00/September 2007 © Semtech Corp.
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ACS8525A LC/P
ADVANCED COMMS & SENSING
Pin Description
Table 1 Power Pins
Pin Number
8, 9,
12
22
27
32, 36,
38, 39,
45, 46,
54
4
14, 57
15, 58
7, 10,
11
31, 40,
53
21
1, 3
Symbol
VD1+, VD2+,
VD3+
VDD_DIFF
VDDCLMP
VDD1, VDD2,
VDD3, VDD4,
VDD5, VDD6,
VDD7
VA1+
VA2+, VA3+
AGND3, AGND4
DGND1, DGND2,
DGND3
DGND4, DGND5,
DGND6
GND_DIFF
AGND1, AGND2
P
P
P
P
I/O
P
P
P
P
Type
-
-
-
-
Description
Supply Voltage: Digital supply to gates in analog section, +3.3 Volts
±5%.
Supply Voltage: Digital supply for differential output pins 19 and 20,
+3.3 Volts ±5%.
Digital Supply for input over-voltage clamping to +3.3 volts. Leave
floating for no clamping.
Supply Voltage: Digital supply to logic, +3.3 Volts ±5%.
FINAL
DATASHEET
P
P
-
-
-
-
-
-
-
Supply Voltage: Analog supply to clock multiplying PLL,
+3.3 Volts ±5%.
Supply Voltage: Analog supply to output PLLs APLL2 and APPL1,
+3.3 Volts ±5%.
Supply Ground: Analog ground for output PLLs APLL2 and APPL1.
Supply Ground: Digital ground for components in PLLs.
Supply Ground: Digital ground for logic.
Supply Ground: Digital ground for differential ports.
Supply Ground: Analog grounds.
Note...I = Input, O = Output, P = Power, TTL
U
= TTL input with pull-up resistor, TTL
D
= TTL input with pull-down resistor.
Table 2 Internally Connected
Pin Number
2, 16, 60, 61,
62, 63
55, 59
Symbol
IC1, IC2, IC3, IC4,
IC5, IC6,
NC1, NC2
I/O
-
-
Type
-
-
Description
Internally Connected: Leave to float.
Not Connected: Leave to float.
Table 3 Other Pins
Pin Number
5
6
13
17
Symbol
INTREQ
REFCLK
SRCSW
FrSync
I/O
O
I
I
O
Type
TTL/CMOS
TTL
TTL
D
TTL/CMOS
Description
Interrupt Request: Active
High/Low
software Interrupt output.
Reference Clock: 12.800 MHz (refer to section headed Local Oscillator
Clock).
Source Switching: Force Fast Source Switching on SEC1 and SEC2.
Output Reference: 8 kHz Frame Sync output.
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