TRU050GCCHA13.824 datasheet, PDF

Datasheet> All Categories > Analog mixed-signal IC> The signal circuit> TRU050GCCHA13.824

TRU050GCCHA13.824: DescriptionPhase Locked Loop, CDSO16, ROHS COMPLIANT, HERMETIC SEALED, CERAMIC, SMD, DIP-16; CategoryAnalog mixed-signal IC The signal circuit; File Size173KB，14 Pages; ManufacturerVectron International, Inc.; Websitehttp://www.vectron.com/; Environmental Compliance

Download Datasheet Parametric View All

TRU050GCCHA13.824 Overview

Phase Locked Loop, CDSO16, ROHS COMPLIANT, HERMETIC SEALED, CERAMIC, SMD, DIP-16

TRU050GCCHA13.824 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	SOIC
package instruction	SOP,
Contacts	16
Reach Compliance Code	compliant
Analog Integrated Circuits - Other Types	PHASE LOCKED LOOP
JESD-30 code	R-CDSO-G16
JESD-609 code	e4
length	20.32 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	4.69 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	GOLD OVER NICKEL
Terminal form	GULL WING
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
width	7.88 mm
Base Number Matches	1

Preview

Download Datasheet

View All

TRU050

Complete VCXO based Phase-Locked Loop

Features

•

Output Frequencies to 65.536 MHz

•

5.0 V or 3.3Vdc Operation

•

Tri-State Output

•

Holdover on Loss of Signal Alarm

•

VCXO with CMOS Outputs

•

0/70° or –40/85°C Temperature Range

•

Ceramic SMD Package

•

RoHS/Lead Free Compliant

The TRU050, VCXO based PLL

Description

The VI TRU050 is a user-configurable crystal-

based PLL integrated circuit. It includes a digital

phase detector, op-amp, VCXO and additional

integrated functions for use in digital

synchronization applications. Loop filter software

is available as well SPICE models for circuit

simulation.

Applications

•

Frequency Translation

•

Clock Smoothing

•

NRZ Clock Recovery

•

DSLAM, ADM, ATM, Aggregation, Optical

Switching/Routing, Base Station

•

Low Jitter PLL’s

Figure 1. TRU050 Block Diagram

Vectron International, 267 Lowell Rd, Hudson NH 03051-4916

Page 1 of 14

Tel: 1-88-VECTRON-1

•

Web:

www.vectron.com

Rev : 06Jan2006

TRU050, VCXO Based PLL

TRU050 Theory of Operation

Phase Detector

The phase detector has two buffered inputs, DATAIN and CLKIN, which are designed to switch at 1.4

volts. DATAIN is designed to accept an NRZ data stream but may also be used for clock signals which

have about a 50% duty cycle. CLKIN is connected to OUT1 or OUT2, or a divided version of one of these

outputs. CLKIN and DATAIN and are protected by ESD diodes and should not exceed the power supply

voltage or ground by more than a few hundred millivolts.

The phase detector is basically a latched flip flop/exclusive-or gate/differential amplifier filter design to

produce a DC signal proportional to the phase between the CLKIN and DATAIN signals, see figure 4 for a

block diagram and figure 5 for a open loop transfer curve. This simplies the PLL design as the designer

does not have to filter narrow pulse signal to a DC level. Under locked conditions the rising edge CLKIN

will be centered in the middle of the DATAIN signal, see figure 6.

The phase detector gain is 0.53V/rad x data density for 5volt operation, and 0.35V/rad x data density for

3.3 volt operation. Data density = 1.0 for clock signals and is system dependent on coding and design

for NRZ signals, but 0.25 could be used as a starting point for data density.

The phase detector output is a DC signal for DATAIN frequencies greater than 1MHz but produces

signficant ripple when inputs are less than 200kHz. Additional filtering is required for low input frequency

applications such as 8kHz frequency translation, see figures 8 and 9.

Under closed loop conditions the active filter has a blocking capacitor which provides a very high DC

gain, so under normal locked conditions and input frequencies >1MHz, PHO will be about V

/2 and will

not vary signifigantly with changes in input frequency (within lock range). The control (voltage pin 1) will

vary according to the input frequency offset, but PHO will remain relatively constant.

Data In

(pin 7)

Clock In

(pin 9)

30 kΩ

20 kΩ

PHO

(pin 6)

Gain = 5 V / 2π

Gain = 2 / 3

Figure 4. Simplified Phase Detector Block Diagram

Vectron International, 267 Lowell Rd, Hudson NH 03051-4916

Page 4 of 14

Tel: 1-88-VECTRON-1

•

Web:

www.vectron.com

Rev : 06Jan2006

Recommended Resources

Single-chip Dolby Logic directional surround sound decoding circuit (CXD2719Q)

Angel JD-26TK-J type warm water dispenser circuit diagram

Triangular wave-square wave-sine wave generator circuit diagram using multiplier

555 multi-function infrared remote control circuit

Single-stage single-frequency amplifier circuit for portable television receivers

About downloading information: When people upload materials, they don't indicate it. This leads to downloading a lot of useless stuff. Suggestion: When posting, write the level of the material, such as advanced, intermediate, begin...; heningbo Suggestions & Announcements

Wireless receiving decoding program based on STM32 and hs1527, ev1527, rt1527, fp1527: 1527 data frame structureThe wireless remote control coding is divided into two categories in terms of coding type. One is fixed code, that is, the address of the coding chip is unchanged, and the chi...; gandong stm32/stm8

IAR installation issues: Why does the prompt "ＦＥＴ－Ｒ４４４ is not a valid WIN32 application" appear when I install ＩＡＲＦＥＴ－Ｒ４４４? I don't know what the problem is? Can any expert please give me some advice?...; Jamie Microcontroller MCU

How to reduce power consumption of 2410+CE5.0: My system is S3C2410 plus CE5.0. The problem I am facing now is that the power consumption is too high. When the screen backlight is turned off, the current is 100mA. A battery of more than 1,000 mAh ...; svfya Embedded System

STC12C5608AD conversion problem: STC12C5608AD has 8 AD conversion ports P1.0~P1.7. If 3 of them are needed to measure current, voltage and temperature, how to call them separately?...; gaodesign MCU

TCP/IP sends bmp picture problem (problem in reading bmp file): Yesterday I called up the program to send files. There was no problem sending files with only a few characters in the content. Today I wanted to send a bmp picture to the PC (it was a frame of picture...; liao_0222 Embedded System

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components