EPF10K100AFI484-3 datasheet, PDF

EPF10K100AFI484-3: DescriptionLoadable PLD, 17ns, CMOS, PBGA484, FINE LINE, BGA-484; CategoryProgrammable logic devices Programmable logic; File Size2MB，136 Pages; ManufacturerAltera (Intel)

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EPF10K100AFI484-3 Overview

Loadable PLD, 17ns, CMOS, PBGA484, FINE LINE, BGA-484

Parameter Name	Attribute value
Parts packaging code	BGA
package instruction	BGA,
Contacts	484
Reach Compliance Code	unknown
JESD-30 code	S-PBGA-B484
JESD-609 code	e1
length	23 mm
Dedicated input times	4
Number of I/O lines	369
Number of terminals	484
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	4 DEDICATED INPUTS, 369 I/O
Output function	REGISTERED
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Programmable logic type	LOADABLE PLD
propagation delay	17 ns
Certification status	Not Qualified
Maximum seat height	2.1 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	23 mm
Base Number Matches	1

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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