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IDT70V3579S5BCG

Description
Dual-Port SRAM, 32KX36, 5ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, GREEN, BGA-256
Categorystorage    storage   
File Size181KB,17 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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IDT70V3579S5BCG Overview

Dual-Port SRAM, 32KX36, 5ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, GREEN, BGA-256

IDT70V3579S5BCG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Parts packaging codeBGA
package instructionLBGA, BGA256,16X16,40
Contacts256
Reach Compliance Codecompliant
ECCN code3A991.B.2.A
Maximum access time5 ns
Other featuresPIPELINED OUTPUT MODE, SELF-TIMED WRITE CYCLE
Maximum clock frequency (fCLK)100 MHz
I/O typeCOMMON
JESD-30 codeS-PBGA-B256
JESD-609 codee1
length17 mm
memory density1179648 bit
Memory IC TypeDUAL-PORT SRAM
memory width36
Humidity sensitivity level3
Number of functions1
Number of ports2
Number of terminals256
word count32768 words
character code32000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX36
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLBGA
Encapsulate equivalent codeBGA256,16X16,40
Package shapeSQUARE
Package formGRID ARRAY, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
power supply2.5/3.3,3.3 V
Certification statusNot Qualified
Maximum seat height1.7 mm
Minimum standby current3.15 V
Maximum slew rate0.36 mA
Maximum supply voltage (Vsup)3.45 V
Minimum supply voltage (Vsup)3.15 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Silver/Copper (Sn/Ag/Cu)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
width17 mm
Base Number Matches1
HIGH-SPEED 3.3V 32K x 36
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
IDT70V3579S
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 4.2/5/6ns (max.)
– Industrial: 5ns (max)
Pipelined output mode
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
– Fast 4.2ns clock to data out
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
address inputs @ 133MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, single 3.3V (±150mV) power supply for
core
LVTTL compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os and control signals on each port
Industrial temperature range (-40°C to +85°C) is
available for selected speeds
Available in a 208-pin Plastic Quad Flatpack (PQFP) and
208-pin fine pitch Ball Grid Array, and 256-pin Ball Grid
Array
Green parts available, see ordering information
Functional Block Diagram
BE
3L
BE
3R
BE
2L
BE
1L
BE
0L
BE
2R
BE
1R
BE
0R
R/W
L
B
W
0
L
B
W
1
L
B B
WW
2 3
L L
B
W
3
R
BB
WW
2 1
RR
B
W
0
R
R/W
R
CE
0L
CE
1L
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
OE
R
32K x 36
MEMORY
ARRAY
I/O
0L
- I/O
35L
Din_L
Din_R
I/O
0R
- I/O
35R
CLK
L
A
14L
A
0L
CNTRST
L
ADS
L
CNTEN
L
CLK
R
,
Counter/
Address
Reg.
A
14R
ADDR_L
ADDR_R
Counter/
Address
Reg.
A
0R
CNTRST
R
ADS
R
CNTEN
R
4830 tbl 01
FEBRUARY 2006
1
©2006 Integrated Device Technology, Inc.
DSC 4830/15

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Description Dual-Port SRAM, 32KX36, 5ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, GREEN, BGA-256 Dual-Port SRAM, 32KX36, 5ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, GREEN, MO-205EAG, FBGA-208 Dual-Port SRAM, 32KX36, 6ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, GREEN, MO-205EAG, FBGA-208 Dual-Port SRAM, 32KX36, 5ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, GREEN, MO-205EAG, FBGA-208 Dual-Port SRAM, 32KX36, 6ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM HEIGHT, GREEN, PLASTIC, MO-143FA-1, QFP-208 Dual-Port SRAM, 32KX36, 5ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM HEIGHT, GREEN, PLASTIC, MO-143FA-1, QFP-208 Dual-Port SRAM, 32KX36, 5ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM HEIGHT, GREEN, PLASTIC, MO-143FA-1, QFP-208 Dual-Port SRAM, 32KX36, 6ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, GREEN, BGA-256 Dual-Port SRAM, 32KX36, 4.2ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM HEIGHT, GREEN, PLASTIC, MO-143FA-1, QFP-208
Is it lead-free? Lead free Lead free Lead free Lead free Lead free Lead free Lead free Lead free Lead free
Is it Rohs certified? conform to conform to conform to conform to conform to conform to conform to conform to conform to
Parts packaging code BGA BGA BGA BGA QFP QFP QFP BGA QFP
package instruction LBGA, BGA256,16X16,40 LFBGA, BGA208,17X17,32 LFBGA, BGA208,17X17,32 LFBGA, BGA208,17X17,32 FQFP, QFP208,1.2SQ,20 FQFP, QFP208,1.2SQ,20 FQFP, QFP208,1.2SQ,20 LBGA, BGA256,16X16,40 FQFP, QFP208,1.2SQ,20
Contacts 256 208 208 208 208 208 208 256 208
Reach Compliance Code compliant compliant compliant compliant compliant compliant compliant compliant compliant
ECCN code 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A
Maximum access time 5 ns 5 ns 6 ns 5 ns 6 ns 5 ns 5 ns 6 ns 4.2 ns
Other features PIPELINED OUTPUT MODE, SELF-TIMED WRITE CYCLE PIPELINED OUTPUT MODE, SELF-TIMED WRITE CYCLE PIPELINED OUTPUT MODE, SELF-TIMED WRITE CYCLE PIPELINED OUTPUT MODE, SELF-TIMED WRITE CYCLE PIPELINED OUTPUT MODE, SELF-TIMED WRITE CYCLE PIPELINED OUTPUT MODE, SELF-TIMED WRITE CYCLE PIPELINED OUTPUT MODE, SELF-TIMED WRITE CYCLE PIPELINED OUTPUT MODE, SELF-TIMED WRITE CYCLE PIPELINED OUTPUT MODE, SELF-TIMED WRITE CYCLE
Maximum clock frequency (fCLK) 100 MHz 100 MHz 83 MHz 100 MHz 83 MHz 100 MHz 100 MHz 83 MHz 133 MHz
I/O type COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON
JESD-30 code S-PBGA-B256 S-PBGA-B208 S-PBGA-B208 S-PBGA-B208 S-PQFP-G208 S-PQFP-G208 S-PQFP-G208 S-PBGA-B256 S-PQFP-G208
JESD-609 code e1 e1 e1 e1 e3 e3 e3 e1 e3
length 17 mm 15 mm 15 mm 15 mm 28 mm 28 mm 28 mm 17 mm 28 mm
memory density 1179648 bit 1179648 bit 1179648 bit 1179648 bit 1179648 bit 1179648 bit 1179648 bit 1179648 bit 1179648 bit
Memory IC Type DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM
memory width 36 36 36 36 36 36 36 36 36
Humidity sensitivity level 3 3 3 3 3 3 3 3 3
Number of functions 1 1 1 1 1 1 1 1 1
Number of ports 2 2 2 2 2 2 2 2 2
Number of terminals 256 208 208 208 208 208 208 256 208
word count 32768 words 32768 words 32768 words 32768 words 32768 words 32768 words 32768 words 32768 words 32768 words
character code 32000 32000 32000 32000 32000 32000 32000 32000 32000
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 70 °C 70 °C 70 °C 85 °C 70 °C 70 °C 85 °C 70 °C 70 °C
organize 32KX36 32KX36 32KX36 32KX36 32KX36 32KX36 32KX36 32KX36 32KX36
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code LBGA LFBGA LFBGA LFBGA FQFP FQFP FQFP LBGA FQFP
Encapsulate equivalent code BGA256,16X16,40 BGA208,17X17,32 BGA208,17X17,32 BGA208,17X17,32 QFP208,1.2SQ,20 QFP208,1.2SQ,20 QFP208,1.2SQ,20 BGA256,16X16,40 QFP208,1.2SQ,20
Package shape SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE
Package form GRID ARRAY, LOW PROFILE GRID ARRAY, LOW PROFILE, FINE PITCH GRID ARRAY, LOW PROFILE, FINE PITCH GRID ARRAY, LOW PROFILE, FINE PITCH FLATPACK, FINE PITCH FLATPACK, FINE PITCH FLATPACK, FINE PITCH GRID ARRAY, LOW PROFILE FLATPACK, FINE PITCH
Parallel/Serial PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
Peak Reflow Temperature (Celsius) 260 260 260 260 260 260 260 260 260
power supply 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 1.7 mm 1.7 mm 1.7 mm 1.7 mm 4.1 mm 4.1 mm 4.1 mm 1.7 mm 4.1 mm
Minimum standby current 3.15 V 3.15 V 3.15 V 3.15 V 3.15 V 3.15 V 3.15 V 3.15 V 3.15 V
Maximum slew rate 0.36 mA 0.36 mA 0.31 mA 0.415 mA 0.31 mA 0.36 mA 0.415 mA 0.31 mA 0.46 mA
Maximum supply voltage (Vsup) 3.45 V 3.45 V 3.45 V 3.45 V 3.45 V 3.45 V 3.45 V 3.45 V 3.45 V
Minimum supply voltage (Vsup) 3.15 V 3.15 V 3.15 V 3.15 V 3.15 V 3.15 V 3.15 V 3.15 V 3.15 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
surface mount YES YES YES YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL INDUSTRIAL COMMERCIAL COMMERCIAL INDUSTRIAL COMMERCIAL COMMERCIAL
Terminal surface Tin/Silver/Copper (Sn/Ag/Cu) Tin/Silver/Copper (Sn/Ag/Cu) Tin/Silver/Copper (Sn/Ag/Cu) Tin/Silver/Copper (Sn/Ag/Cu) MATTE TIN MATTE TIN MATTE TIN Tin/Silver/Copper (Sn/Ag/Cu) MATTE TIN
Terminal form BALL BALL BALL BALL GULL WING GULL WING GULL WING BALL GULL WING
Terminal pitch 1 mm 0.8 mm 0.8 mm 0.8 mm 0.5 mm 0.5 mm 0.5 mm 1 mm 0.5 mm
Terminal location BOTTOM BOTTOM BOTTOM BOTTOM QUAD QUAD QUAD BOTTOM QUAD
Maximum time at peak reflow temperature 30 30 30 30 30 30 30 30 30
width 17 mm 15 mm 15 mm 15 mm 28 mm 28 mm 28 mm 17 mm 28 mm
Base Number Matches 1 1 1 1 1 - - - -
Maker - IDT (Integrated Device Technology) - IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)

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Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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