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RP14100A-1CQ256E

Description
Field Programmable Gate Array, 1377 CLBs, 25000 Gates, 100MHz, CQFP256, CAVITY-UP, CERAMIC, QFP-256
CategoryProgrammable logic devices    Programmable logic   
File Size621KB,38 Pages
ManufacturerActel
Websitehttp://www.actel.com/
Download Datasheet Parametric Compare View All

RP14100A-1CQ256E Overview

Field Programmable Gate Array, 1377 CLBs, 25000 Gates, 100MHz, CQFP256, CAVITY-UP, CERAMIC, QFP-256

RP14100A-1CQ256E Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
package instructionCAVITY-UP, CERAMIC, QFP-256
Reach Compliance Codecompliant
maximum clock frequency100 MHz
Combined latency of CLB-Max3 ns
JESD-30 codeS-CQFP-F256
JESD-609 codee0
length36 mm
Configurable number of logic blocks1377
Equivalent number of gates25000
Number of terminals256
organize1377 CLBS, 25000 GATES
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeGQFF
Package shapeSQUARE
Package formFLATPACK, GUARD RING
Peak Reflow Temperature (Celsius)225
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height3.06 mm
Nominal supply voltage5 V
surface mountYES
Terminal surfaceTIN LEAD
Terminal formFLAT
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width36 mm
Base Number Matches1
Pr el i mi na r y v 1. 2
RadTolerant RAD-PAK
®
Field Programmable Gate Arrays
Featur es
Radiation Characteristics
• Highly Predictable Performance with 100% Automatic
Place and Route
• 100% Resource Utilization with 100% Pin-Locking
• Secure Programming Technology Prevents Reverse
Engineering and Design Theft
• Permanently Programmed for Operation on Power-Up
• Unique In-System Diagnostic and Debug Facility with
Silicon Explorer
• Actel Designer Series Design Tools, Supported by
Cadence, Exemplar, Mentor Graphics, Model Technology,
Synopsys, Synplicity and Viewlogic Design Entry and
Simulation Tools
Gen era l D es cr i pt i on
• RAD-PAK
®
Package Technology from Space Electronics,
Inc.
• Improved Total Ionizing Dose (TID) Survivability
– Can Improve TID 2-10x Over Standard Package
– Can Achieve > 100 KRads (Si) in Some Orbits
• Packages: 172-Pin and 256-Pin RAD-PAK
®
Ceramic Quad
Flat Pack
• Offered as E-Flow (Actel Space Level Flow) and Class B
High Density and Performance
• 16,000 and 20,000 Gates
• 8,000 and 10,000 ASIC Equivalent Gates
• Up to 85 MHz On-Chip Performance
• Up to 228 User I/Os
• Up to Four Fast, Low-Skew Clock Networks
Easy Logic Integration
• Non-Volatile, User Programmable
• Pin-Compatible Commercial Devices Available for
Prototyping
P roduct Fami l y P ro file
Device
Gates
ASIC Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Package
20-Pin PAL Equivalent Packages
Logic Modules
S-Modules
C-Modules
User I/Os
CQFP Package Pin Count
Performance System Speed (Maximum)
Ordering Information
Part Number (Class B)
Part Number (E-Flow)
Commercial Equivalent for Prototyping
Actel builds the most reliable field programmable gate arrays
(FPGAs) in the industry, with overall antifuse reliability
ratings of less than 10 failures-in-time (FITs), corresponding
to a useful life of more than 40 years. Actel FPGAs are
production-proven, with more than five million devices
shipped and more than one trillion antifuses manufactured.
Actel devices are fully tested prior to shipment, with an
out-going defect level of only 122 ppm. (Further reliability
data is available in the “Actel Device Reliability Report” at
http://www.actel.com/hirel).
RP1280A
16,000
8,000
20,000
200
80
1,232
624
608
140
172
40 MHz
RP1280A-CQ172B
RP1280A-CQ172E
A1280A-CQ172C
RP14100A
20,000
10,000
25,000
250
100
1,377
697
680
228
256
60 MHz
RP14100A-CQ256B
RP14100A-CQ256E
A14100A-CQ256C
O cto b e r 1 9 9 9
1
© 1999 Actel Corporation

RP14100A-1CQ256E Related Products

RP14100A-1CQ256E RP14100A-1CQ256B RP14100A-CQ256B RP14100A-CQ256E RP1280A-1CQG172E
Description Field Programmable Gate Array, 1377 CLBs, 25000 Gates, 100MHz, CQFP256, CAVITY-UP, CERAMIC, QFP-256 Field Programmable Gate Array, 1377 CLBs, 25000 Gates, 100MHz, CQFP256, CAVITY-UP, CERAMIC, QFP-256 Field Programmable Gate Array, 1377 CLBs, 25000 Gates, 85MHz, CQFP256, CAVITY-UP, CERAMIC, QFP-256 Field Programmable Gate Array, 1377 CLBs, 25000 Gates, 85MHz, CQFP256, CAVITY-UP, CERAMIC, QFP-256 Field Programmable Gate Array, 1232 CLBs, 20000 Gates, 60MHz, CQFP172, CERAMIC, RAD-PAK, QFP-172
package instruction CAVITY-UP, CERAMIC, QFP-256 CAVITY-UP, CERAMIC, QFP-256 CAVITY-UP, CERAMIC, QFP-256 CAVITY-UP, CERAMIC, QFP-256 CERAMIC, RAD-PAK, QFP-172
Reach Compliance Code compliant compliant compliant unknown compliant
maximum clock frequency 100 MHz 100 MHz 85 MHz 85 MHz 60 MHz
Combined latency of CLB-Max 3 ns 3 ns 3.5 ns 3.5 ns 5.2 ns
JESD-30 code S-CQFP-F256 S-CQFP-F256 S-CQFP-F256 S-CQFP-F256 S-CQFP-F172
length 36 mm 36 mm 36 mm 36 mm 29.21 mm
Configurable number of logic blocks 1377 1377 1377 1377 1232
Equivalent number of gates 25000 25000 25000 25000 20000
Number of terminals 256 256 256 256 172
organize 1377 CLBS, 25000 GATES 1377 CLBS, 25000 GATES 1377 CLBS, 25000 GATES 1377 CLBS, 25000 GATES 1232 CLBS, 20000 GATES
Package body material CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
encapsulated code GQFF GQFF GQFF GQFF GQFF
Package shape SQUARE SQUARE SQUARE SQUARE SQUARE
Package form FLATPACK, GUARD RING FLATPACK, GUARD RING FLATPACK, GUARD RING FLATPACK, GUARD RING FLATPACK, GUARD RING
Programmable logic type FIELD PROGRAMMABLE GATE ARRAY FIELD PROGRAMMABLE GATE ARRAY FIELD PROGRAMMABLE GATE ARRAY FIELD PROGRAMMABLE GATE ARRAY FIELD PROGRAMMABLE GATE ARRAY
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 3.06 mm 3.06 mm 3.06 mm 3.06 mm 3.7084 mm
Nominal supply voltage 5 V 5 V 5 V 5 V 5 V
surface mount YES YES YES YES YES
Terminal form FLAT FLAT FLAT FLAT FLAT
Terminal pitch 0.5 mm 0.5 mm 0.5 mm 0.5 mm 0.635 mm
Terminal location QUAD QUAD QUAD QUAD QUAD
width 36 mm 36 mm 36 mm 36 mm 29.21 mm
Is it Rohs certified? incompatible incompatible incompatible - conform to
JESD-609 code e0 e0 e0 - e4
Peak Reflow Temperature (Celsius) 225 225 225 - NOT SPECIFIED
Terminal surface TIN LEAD TIN LEAD TIN LEAD - GOLD
Maximum time at peak reflow temperature 30 30 30 - NOT SPECIFIED
Base Number Matches 1 1 1 1 -

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