January 2009
H Y S 72 D6 4 301E B R– [ 5 / 6 ] – D
H Y S 72 D1 2 8300E BR– [ 5 / 6 ] – D
H Y S 72 D1 2 8321E BR– [ 5 / 6 ] – D
H Y S 72 D2 5 6320E BR– [ 5 / 6 ] – D
1 8 4 - P i n R e g i s t e r e d D o u b l e - D a t a - R a t e SD R A M M o d u l e
RDIMM
RoHS Compliant
Internet Data Sheet
Rev. 1.00
Internet Data Sheet
HYS72D[64/128/256]xxxEBR–[5/6]–D
Registered Double-Data-Rate SDRAM Module
HYS72D64301EBR–[5/6]–D, HYS72D128300EBR–[5/6]–D, HYS72D128321EBR–[5/6]–D, HYS72D256320EBR–[5/6]–D
Revision History: 2009-01, Rev. 1.00
Page
All
13 - 14
All
Subjects (major changes since last revision)
Metadata change and adapted to internet edition.
Added IDD values.
New Document.
Previous Revision: Rev. 0.60, 2008-03
Previous Revision: Rev. 0.50, 2007-09
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qag_techdoc_A4, 4.22, 2008-07-22
12052007-K8PV-LLU3
2
Internet Data Sheet
HYS72D[64/128/256]xxxEBR–[5/6]–D
Registered Double-Data-Rate SDRAM Module
1
Overview
1.1
Features
• 184-Pin Registered 8-Byte Dual-In-Line DDR SDRAM Module for PC, Workstation and Server main memory applications
• One rank 64M
×72,
128M
×72,
and two ranks 128M
×72,
256M
×72
module organization, and 128M
×4,
64M
×8
chip
organization
• Standard Double-Data-Rate Synchronous DRAMs (DDR SDRAM) with a single + 2.5 V (± 0.2 V) power supply and +2.6
(± 0.1 V) power supply for DDR400
• Built with DDR SDRAMs in FBGA 60 package
• Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• RAS-lockout supported
t
RAP
=
t
RCD
• All inputs and outputs SSTL_2 compatible
• Re-drive for all input signals using register and PLL devices.
• Serial Presence Detect with E
2
PROM
• Low Profile Modules form factor: 133.35 mm
×
28.58 mm (1.1”)
×
4.00 mm and 133.35 mm
×
30.48 mm (1.2”)
• Standard reference card layout Raw Card A, B, C and F
• Gold plated contacts
• RoHS Compliant Product
1)
TABLE 1
Performance
Part Number Speed Code
Speed Grade
max. Clock Frequency
Component
Module
@CL3
@CL2.5
@CL2
–5
DDR400B
PC3200–3033
–6
DDR333B
PC2700–2533
166
166
133
Unit
—
—
MHz
MHz
MHz
f
CK3
f
CK2.5
f
CK2
200
166
133
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.00, 2009-01
12052007-K8PV-LLU3
3
Internet Data Sheet
HYS72D[64/128/256]xxxEBR–[5/6]–D
Registered Double-Data-Rate SDRAM Module
1.2
Description
the SDRAM timing. A variety of decoupling capacitors are
mounted on the PC board. The DIMMs feature serial
presence detect based on a serial E
2
PROM device using the
2-pin I
2
C protocol. The first 128 bytes contain factory
programmed configuration data and the second 128 bytes
are made available to the customer.
The HYS72D[64/128/256]xxxEBR–[5/6]–C are low-profile
versions of the standard Registered DIMM modules with 1.1-
inch (28.58 mm) and 1.2-inch (30.40 mm) height for Server
Applications. The low-profile DIMM versions are available as
64M
×72
(512-MB), 128M
×72
(1-GB), and 256M
×72
(2-GB).
The memory array is designed with Double-Data-Rate
Synchronous DRAMs for ECC applications. All control and
address signals are re-driven on the DIMM using register
devices and a PLL for the clock distribution. This reduces
capacitive loading to the system bus, but adds one cycle to
TABLE 2
Ordering Information
Product Type
1)
PC3200 (CL=3)
HYS72D64301EBR–5–D
HYS72D128300EBR–5–D
HYS72D128321EBR–5–D
HYS72D256320EBR–5–D
PC2700 (CL=2.5)
HYS72D64301EBR–6–D
HYS72D128300EBR–6–D
HYS72D128321EBR–6–D
HYS72D256320EBR–6–D
PC2700R–25331–A0
PC2700R–25331–C0
PC2700R–25331–B0
PC2700R–25331–F0
one rank 512-MB, ECC DIMM
one rank 1-GB, ECC DIMM
two ranks 1-GB, ECC DIMM
two ranks 2-GB, ECC DIMM
512-MBit (×8)
512-MBit (×4)
512-MBit (×8)
512-MBit (×4)
PC3200R–30331–A0
PC3200R–30331–C0
PC3200R–30331–B0
PC3200R–30331–F0
one rank 512-MB, ECC DIMM
one rank 1-GB, ECC DIMM
two ranks 1-GB, ECC DIMM
two ranks 2-GB, ECC DIMM
512-MBit (×8)
512-MBit (×4)
512-MBit (×8)
512-MBit (×4)
Compliance Code
2)
Description
SDRAM Technology
1) All product types end with a place code designating the silicon-die revision. Reference information available on request. Example:
HYS72D128300EBR–5–D, indicating Rev.D die are used for SDRAM components.
2) The Compliance Code is printed on the module labels and describes the speed sort (for example “PC2700R”), the latencies (for example
“25331” means CAS latency of 2.5 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Precharge latency of 3 clocks), SPD
code definition version 1, and the Raw Card used for this module.
TABLE 3
Address Format
Density
512-MB
1-GB
1-GB
2-GB
Organization
64M
×72
128M
×72
128M
×72
256M
×72
Memory
Ranks
1
1
2
2
SDRAMs
64M
×8
128M
×4
64M
×8
128M
×4
# of
SDRAMs
9
18
18
36
# of row/bank/
column bits
13/2/11
13/2/12
13/2/11
13/2/12
Refresh
8K
8K
8K
8K
Period
64 ms
64 ms
64 ms
64 ms
Interval
7.8 ms
7.8 ms
7.8 ms
7.8 ms
Rev. 1.00, 2009-01
12052007-K8PV-LLU3
4
Internet Data Sheet
HYS72D[64/128/256]xxxEBR–[5/6]–D
Registered Double-Data-Rate SDRAM Module
2
Pin Configuration
2.1
Pin Configuration
The pin configuration of the Registered DDR SDRAM DIMM is listed by function in
Table 4
(184 pins). The abbreviations used
in columns Pin and Buffer Type are explained in
Table 5
and
Table 6
respectively. The pin numbering is depicted in
Chapter 1.
Pin
#
48
43
41
130
I
I
I
I
NC
I
I
NC
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
–
SSTL
SSTL
SSTL
LV-
CMOS
Clock Signal
Complement Clock
Clock Enable Rank 0
Clock Enable Rank 1
Note: 2-rank module
Note: 1-rank module
Chip Select of Rank 0
Chip Select of Rank 1
Note: 2-ranks module
Note: 1-rank module
Row Address Strobe
Column Address Strobe
Write Enable
Register Reset
Forces registered inputs
low
Note: For detailed des-
cription of the
Power Up and
Power
Management see
the Application
Note at the end of
data sheet
Bank Address Bus 1:0
167
NC
A13
NC
I
–
SSTL
118
115
37
32
125
29
122
27
141
Name
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
Pin
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Address Signal 12
Note: Module based on
256 Mbit or larger
dies
Note: 128 Mbit based
module
Address Signal 13
Note: 1 Gbit based
module
Note: Module based on
512 Mbit or smaller
dies
Address Bus 11:0
Function
Address Bus 11:0
TABLE 4
Pin Configuration of RDIMM
Pin
#
Name
Pin
Type
Buffer
Type
Function
Clock Signals
137
138
21
111
CK0
CK0
CKE0
CKE1
NC
157
158
S0
S1
NC
154
65
63
10
RAS
CAS
WE
RESET
Control Signals
NC
NC
–
Data Signals
Address Signals
59
52
BA0
BA1
I
I
SSTL
SSTL
Rev. 1.00, 2009-01
12052007-K8PV-LLU3
5