S29NS-J
128 Megabit (8 M x 16-Bit), 64 Megabit (4 M x 16-Bit),
32 Megabit (2 M x 16-Bit), and 16 Megabit (1 M x 16 Bit),
110 nm CMOS 1.8-Volt only Simultaneous Read/Write,
Burst Mode Flash Memories
Data Sheet
S29NS-J Cover Sheet
Notice to Readers:
This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See
Notice On Data Sheet Designations
for definitions.
Publication Number
S29NS-J_00
Revision
A
Amendment
11
Issue Date
February 7, 2007
D at a
S hee t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or V
IO
range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2
S29NS-J
S29NS-J_00_A11 February 7, 2007
S29NS-J
128 Megabit (8 M x 16-Bit), 64 Megabit (4 M x 16-Bit),
32 Megabit (2 M x 16-Bit), and 16 Megabit (1 M x 16 Bit),
110 nm CMOS 1.8-Volt only Simultaneous Read/Write,
Burst Mode Flash Memories
Data Sheet
Features
Single 1.8 volt read, program and erase (1.7 to 1.95 V)
Multiplexed Data and Address for reduced
I/O count
– A15–A0 multiplexed as DQ15–DQ0
– Addresses are latched by AVD# control input when CE# low
Sector Protection
– Software command sector locking
– WP# protects the two highest sectors
– All sectors locked when A
cc
= V
IL
Handshaking feature
– Provides host system with minimum possible latency by monitoring
RDY
Simultaneous Read/Write operation
– Data can be continuously read from one bank while executing
erase/program functions in other bank
– Zero latency between read and write operations
Supports Common Flash Memory Interface (CFI)
Software command set compatible with JEDEC 42.4
standards
– Backwards compatible with Am29F and Am29LV families
Read access times at 54 MHz (C
L
=30 pF)
– Burst access times of 11/13.5 ns
at industrial temperature range
– Asynchronous random access times
of 65/70 ns
– Synchronous random access times
of 71/87.5 ns
Manufactured on 110 nm process technology
Embedded Algorithms
– Embedded Erase algorithm automatically preprograms and erases
the entire chip or any combination of designated sectors
– Embedded Program algorithm automatically writes and verifies data
at specified addresses
Burst Modes
– Continuous linear burst
– 8/16/32 word linear burst with wrap around
– 8/16/32 word linear burst without wrap around
Data# Polling
– Provides a software method of detecting program and erase
operation completion
Power dissipation (typical values, 8 bits switching, C
L
= 30
pF)
–
–
–
–
Burst Mode Read: 25 mA
Simultaneous Operation: 40 mA
Program/Erase: 15 mA
Standby mode: 9 µA
Erase Suspend/Resume
– Suspends an erase operation to read data from, or program data to,
a sector that is not being erased, then resumes the erase operation
Hardware reset input (RESET#)
– Hardware method to reset the device for reading array data
Sector Architecture
– Four 8 Kword sectors
– Two hundred fifty-five (S29NS128J), one hundred twenty-seven
(S29NS064J),sixty-three (S29NS032J), or thirty-one (S29NS016J)
32 Kword sectors
– Four banks (see next page for sector count and size)
CMOS compatible inputs and outputs
Package
– 48-ball Very Thin FBGA (S29NS128J)
– 44-ball Very Thin FBGA (S29NS064J, S29NS032J, S29NS016J)
Cycling Endurance: 1 million cycles per sector typical
Data Retention: 20 years typical
General Description
The S29NS128J, S29NS064J, S29NS032J and S29NS016J are 128 Mbit, 64 Mbit, 32 Mbit and 16 Mbit 1.8 Volt-only,
Simultaneous Read/Write, Burst Mode Flash memory devices, organized as 8,388,608, 4,194,304, 2,097,152 and 1,048,576.
words of 16 bits each. These devices use a single V
CC
of 1.7 to 1.95 V to read, program, and erase the memory array. A 12.0-
volt A
cc
may be used for faster program performance if desired. These devices can also be programmed in standard
EPROM programmers.
The devices are offered at the following speeds:
Clock Speed
54 MHz
Burst Access (ns)
13.5
Synch. Initial Access (ns)
87.5
Asynchronous Initial Access (ns)
70
Output Loading
30 pF
Publication Number
S29NS-J_00
Revision
A
Amendment
11
Issue Date
February 7, 2007
D at a
S hee t
The devices operate within the temperature range of –25
°C
to +85
°C,
and are offered Very Thin FBGA
packages.
Simultaneous Read/Write Operations with Zero Latency
The Simultaneous Read/Write architecture divides the memory space into four banks. The device allows a
host system to program or erase in one bank, then immediately and simultaneously read from another bank,
with zero latency. This releases the system from waiting for the completion of program or erase operations.
The devices are structured as shown in the following tables:
S29NS128J
Bank A Sectors
Quantity
4
63
32 Mbits total
S29NS064J
Bank A Sectors
Quantity
4
31
16 Mbits total
S29NS032J
Bank A Sectors
Quantity
4
15
8 Mbits total
S29NS016J
Bank A Sectors
Quantity
4
7
4 Mbits total
Size
8 Kwords
32 Kwords
Quantity
8
12 Mbits total
Bank B, C & D Sectors
Size
32 Kwords
Size
8 Kwords
32 Kwords
Quantity
16
24 Mbits total
Bank B, C & D Sectors
Size
32 Kwords
Size
8 Kwords
32 Kwords
Quantity
32
48 Mbits total
Bank B, C & D Sectors
Size
32 Kwords
Size
8 Kwords
32 Kwords
Quantity
64
96 Mbits total
Bank B, C & D Sectors
Size
32 Kwords
The devices use Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output Enable (OE#) to
control asynchronous read and write operations. For burst operations, the devices additionally require Ready
(RDY) and Clock (CLK). This implementation allows easy interface with minimal glue logic to
microprocessors/microcontrollers for high performance read operations.
The devices offer complete compatibility with the
JEDEC 42.4 single-power-supply Flash command set
standard.
Commands are written to the command register using standard microprocessor write timings.
Reading data out of the device are similar to reading from other Flash or EPROM devices.
The host system can detect whether a program or erase operation is complete by using the device
status bit
DQ7 (Data# Polling). After a program or erase cycle has been completed, the device automatically returns to
reading array data.
The
sector erase architecture
allows memory sectors to be erased and reprogrammed without affecting the
data contents of other sectors. The devices are fully erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations
during power transitions. The devices also offer three types of data protection at the sector level. The
sector
4
S29NS-J
S29NS-J_00_A11 February 7, 2007
Data
She et
lock/unlock command sequence
disables or re-enables both program and erase operations in any sector.
When at V
IL
,
WP#
locks the highest two sectors. Finally, when
A
cc
is at V
IL
, all sectors are locked.
The devices offer two power-saving features. When addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby
mode.
Power consumption is greatly reduced in both modes.
February 7, 2007 S29NS-J_00_A11
S29NS-J
5
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