UPD45128441G5-A10L-9JF datasheet, PDF

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UPD45128441G5-A10L-9JF: DescriptionSynchronous DRAM, 32MX4, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54; Categorystorage storage; File Size713KB，88 Pages; ManufacturerELPIDA; Websitehttp://www.elpida.com/en

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UPD45128441G5-A10L-9JF Overview

Synchronous DRAM, 32MX4, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54

UPD45128441G5-A10L-9JF Parametric

Parameter Name	Attribute value
Parts packaging code	TSOP2
package instruction	TSOP2,
Contacts	54
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	6 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PDSO-G54
length	22.22 mm
memory density	134217728 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	4
Number of functions	1
Number of ports	1
Number of terminals	54
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32MX4
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
width	10.16 mm
Base Number Matches	1

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PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

PD45128441, 45128841, 45128163

128M-bit Synchronous DRAM

4-bank, LVTTL

Description

The

PD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access

memories, organized as 8,388,608

4, 4,194,304

4, 2,097,152

4 (word

bit

bank), respectively.

The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.

All inputs and outputs are synchronized with the positive edge of the clock.

The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).

These products are packaged in 54-pin TSOP (II).

Features

•

Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge

•

Pulsed interface

•

Possible to assert random column address in every cycle

•

Quad internal banks controlled by A12 and A13 (Bank Select)

•

Byte control (×16) by LDQM and UDQM

•

Programmable Wrap sequence (Sequential / Interleave)

•

Programmable burst length (1, 2, 4, 8 and full page)

•

Programmable /CAS latency (2 and 3)

•

Automatic precharge and controlled precharge

•

CBR (Auto) refresh and self refresh

• ×4, ×8, ×16

organization

•

Single 3.3 V

0.3 V power supply

•

LVTTL compatible inputs and outputs

•

4,096 refresh cycles / 64 ms

•

Burst termination by Burst stop command and Precharge command

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. M12650EJ9V0DS00 (9th edition)

Date Published March 1999 NS CP (K)

Printed in Japan

The mark

•

shows major revised points.

1997

UPD45128441G5-A10L-9JF Related Products

	UPD45128441G5-A10L-9JF	UPD45128441G5-A10BL-9JF	UPD45128163G5-A10BL-9JF	UPD45128163G5-A10L-9JF	UPD45128841G5-A10L-9JF	UPD45128841G5-A10BL-9JF
Description	Synchronous DRAM, 32MX4, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54	Synchronous DRAM, 32MX4, 7ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54	Synchronous DRAM, 8MX16, 7ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54	Synchronous DRAM, 8MX16, 6ns, MOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54	Synchronous DRAM, 16MX8, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54	Synchronous DRAM, 16MX8, 7ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54
Parts packaging code	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2
package instruction	TSOP2,	TSOP2,	TSOP2,	TSOP2,	TSOP2,	TSOP2,
Contacts	54	54	54	54	54	54
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	6 ns	7 ns	7 ns	6 ns	6 ns	7 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 code	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54
length	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm
memory density	134217728 bit	134217728 bit	134217728 bit	134217728 bit	134217728 bit	134217728 bit
Memory IC Type	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
memory width	4	4	16	16	8	8
Number of functions	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1
Number of terminals	54	54	54	54	54	54
word count	33554432 words	33554432 words	8388608 words	8388608 words	16777216 words	16777216 words
character code	32000000	32000000	8000000	8000000	16000000	16000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	32MX4	32MX4	8MX16	8MX16	16MX8	16MX8
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
self refresh	YES	YES	YES	YES	YES	YES
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	MOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
width	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm
Maker	-	-	ELPIDA	ELPIDA	ELPIDA	ELPIDA

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