MC74HC04A
Hex Inverter
High–Performance Silicon–Gate CMOS
The MC74HC04A is identical in pinout to the LS04 and the
MC14069. The device inputs are compatible with Standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
The device consists of six three–stage inverters.
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MARKING
DIAGRAMS
14
PDIP–14
N SUFFIX
CASE 646
MC74HC04AN
AWLYYWW
1
14
SOIC–14
D SUFFIX
CASE 751A
1
14
Y1
TSSOP–14
DT SUFFIX
CASE 948G
HC
04A
ALYW
HC04A
AWLYWW
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2 to 6V
Low Input Current: 1µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 36 FETs or 9 Equivalent Gates
LOGIC DIAGRAM
A1
1
2
A2
3
4
Y2
A3
5
6
Y3
Y=A
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
A4
9
8
Y4
FUNCTION TABLE
Inputs
Outputs
Y
H
L
A5
11
10
Y5
A
L
H
A6
13
12
Y6
Pinout: 14–Lead Packages
(Top View)
VCC
14
A6
13
Y6
12
A5
11
Y5
10
A4
9
Y4
8
ORDERING INFORMATION
Device
MC74HC04AN
MC74HC04AD
MC74HC04ADR2
Package
PDIP–14
SOIC–14
SOIC–14
TSSOP–14
TSSOP–14
Shipping
2000 / Box
55 / Rail
2500 / Reel
96 / Rail
2500 / Reel
1
A1
2
Y1
3
A2
4
Y2
5
A3
6
Y3
7
GND
MC74HC04ADT
MC74HC04ADTR2
©
Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 8
Publication Order Number:
MC74HC04A/D
MC74HC04A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
ÎÎÎÎ
Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ Î
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
ÎÎÎ
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*
Symbol
VCC
Vin
Parameter
Value
Unit
V
V
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
– 0.5 to VCC + 0.5
±
20
±
25
±
50
750
500
450
Vout
Iin
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
mA
mA
mA
Iout
DC Output Current, per Pin
ICC
PD
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air,
Plastic DIP†
SOIC Package†
TSSOP Package†
mW
Tstg
TL
Storage Temperature
– 65 to + 150
260
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_
C
_
C
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/
_
C from 65
_
to 125
_
C
SOIC Package: – 7 mW/
_
C from 65
_
to 125
_
C
TSSOP Package: – 6.1 mW/
_
C from 65
_
to 125
_
C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
ÎÎÎÎ Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ Î
ÎÎÎÎ Î
ÎÎ Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ Î
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
Symbol
VCC
Parameter
Min
2.0
0
Max
6.0
Unit
V
V
DC Supply Voltage (Referenced to GND)
Vin, Vout
TA
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Figure 1)
VCC
– 55
0
0
0
+ 125
1000
500
400
_
C
ns
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
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2
MC74HC04A
DC CHARACTERISTICS
(Voltages Referenced to GND)
VCC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
|Iout|
≤
2.4mA
|Iout|
≤
4.0mA
|Iout|
≤
5.2mA
3.0
4.5
6.0
2.0
4.5
6.0
|Iout|
≤
2.4mA
|Iout|
≤
4.0mA
|Iout|
≤
5.2mA
3.0
4.5
6.0
6.0
6.0
Guaranteed Limit
–55 to 25°C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
±
0.1
1.0
≤85°C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
±
1.0
10
≤125°C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.20
3.70
5.20
0.1
0.1
0.1
0.40
0.40
0.40
±
1.0
40
µA
µA
V
Unit
V
Symbol
VIH
Parameter
Minimum High–Level Input
Voltage
Condition
Vout = 0.1V or VCC –0.1V
|Iout|
≤
20µA
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1V or VCC – 0.1V
|Iout|
≤
20µA
V
VOH
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
≤
20µA
Vin =VIH or VIL
V
VOL
Maximum Low–Level Output
Voltage
Vin = VIH or VIL
|Iout|
≤
20µA
Vin = VIH or VIL
Iin
ICC
Maximum Input Leakage
Current
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Vin = VCC or GND
Iout = 0µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS
(CL = 50pF, Input tr = tf = 6ns)
Symbol
tPLH,
tPHL
Parameter
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
VCC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
Guaranteed Limit
–55 to 25°C
75
30
15
13
75
27
15
13
10
≤85°C
95
40
19
16
95
32
19
16
10
≤125°C
110
55
22
19
110
36
22
19
10
Unit
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
ns
Cin
Maximum Input Capacitance
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Inverter)*
20
pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
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3
MC74HC04A
tf
90%
50%
10%
tPLH
90%
OUTPUT Y
50%
10%
tTLH
tTHL
tPHL
tr
VCC
INPUT A
GND
Figure 1. Switching Waveforms
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
Figure 2. Test Circuit
A
Y
Figure 3. Expanded Logic Diagram
(1/6 of the Device Shown)
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4
MC74HC04A
PACKAGE DIMENSIONS
PDIP–14
N SUFFIX
CASE 646–06
ISSUE L
14
8
B
1
7
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.300 BSC
0
_
10
_
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.62 BSC
0
_
10
_
0.39
1.01
A
F
C
N
H
G
D
SEATING
PLANE
L
J
K
M
SOIC–14
D SUFFIX
CASE 751A–03
ISSUE F
–A–
14
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–B–
1
7
P
7 PL
0.25 (0.010)
M
B
M
G
C
R
X 45
_
F
–T–
SEATING
PLANE
D
14 PL
0.25 (0.010)
K
M
M
S
J
T B
A
S
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
_
7
_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
_
7
_
0.228
0.244
0.010
0.019
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