BU-65142F1-800Q datasheet, PDF

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BU-65142F1-800Q: DescriptionMil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CQFP78, 45.70 X 53.30 MM, 5.30 MM HEIGHT, CERAMIC, FP-78; CategoryThe embedded processor and controller Microcontrollers and processors; File Size265KB，28 Pages; ManufacturerData Device Corporation

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BU-65142F1-800Q Overview

Mil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CQFP78, 45.70 X 53.30 MM, 5.30 MM HEIGHT, CERAMIC, FP-78

BU-65142F1-800Q Parametric

Parameter Name	Attribute value
Parts packaging code	QFP
package instruction	QFF,
Contacts	78
Reach Compliance Code	unknown
Address bus width	11
boundary scan	NO
maximum clock frequency	16 MHz
letter of agreement	MIL STD 1553B
Data encoding/decoding methods	BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	0.125 MBps
External data bus width	16
JESD-30 code	R-CQFP-F78
low power mode	NO
Number of serial I/Os	2
Number of terminals	78
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QFF
Package shape	RECTANGULAR
Package form	FLATPACK
Certification status	Not Qualified
Maximum seat height	5.33 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	QUAD
total dose	300k Rad(Si) V
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553
Base Number Matches	1

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BU-65142 series*

MIL-STD-1553 DUAL REDUNDANT

REMOTE TERMINAL HYBRID

DESCRIPTION

The BU-65142 Series is a Hi-Rel

radiation tolerent complete dual

redundant MIL-STD-1553 Remote

Terminal Unit (RTU). The device is

based upon two DDC custom ICs,

which includes two monolithic bi-

polar low power transceivers and

one RiCmos protocol containing

data buffers and timing control logic.

It supports all 13 mode codes for dual

redundant operation, any combina-

tion of which can be illegalized.

Parallel data transfers are accom-

plished with a DMA type handshak-

ing, compatible with most CPU

types. Data transfers to/from mem-

ory are simplified by the latched

command word and word count out-

puts.

Error detection and recovery are

enhanced by BU-65142 Series spe-

cial features. A 14-bit built-in-test

word register stores RTU information,

and sends it to the Bus Controller in

response to the Mode Command

Transmit Bit Word. The BU-65142

Series performs continuous on-line

wraparound self-test, and provides

four error flags to the host CPU.

Inputs are provided for host CPU con-

trol of 6 bits of the RTU Status Word.

Its integrated hermetic package,

-55°C to +125°C operating tempera-

ture range, and complete RTU opera-

tion make the BU-65142 ideal for

MIL-STD-1553 applications requiring

hardware or microprocessor subsys-

tems.

FEATURES

•

Radiation Tolerant to 300 krad

•

Complete Integrated Remote

Terminal Including:

–Dual Low-Power Transceivers

–Complete RT Protocol

•

Multiple Ordering Options;

+5V (Only), +5V/-15V, and +5V/-12V

•

Direct Interface to Systems With

No Processor

•

Space Qualified

•

High Reliability Screening

(Note:

BU-65142 is NOT recommended for new design, consult factory or local representative for more information)

DATA

BUS A

TRANSCEIVER

ENCODER/

DECODER

BIT

PROCESSOR

BUFFER

DB0-DB15

BUF ENA

DTREQ

DTGRT

DTACK

DTSTR

R/W

WATCHDOG

TIMEOUT

TRANSFER

CONTROLS

DATA

BUS B

TRANSCEIVER

ENCODER/

DECODER

BIT

PROCESSOR

CURRENT

WORD

COUNTER

PROTOCOL

SEQUENCER

AND

CONTROL

LOGIC

A0-A4

A5-A10

DAT/CMD

ILL CMD (ME)

SS REQ

ADBC

RT FLAG

SS BUSY

SS FLAG

MESS ERR

RT FAIL

HS FAIL

RTADD ERR

NBGT

INCMD

BITEN

STATEN

GBR

COMMAND

LATCH

RT ADDRESS

PARITY

STATUS

16 MHz CLOCK

ERROR FLAGS

TIMING FLAGS

DDC CUSTOM CHIP

D-RAD

FIGURE 1. BU-65142 SERIES BLOCK DIAGRAM

1988, 1999 Data Device Corporation

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