Very Low Power CMOS SRAM
1M X 8 bit
Pb-Free and Green package materials are compliant to RoHS
BS62LV8001
FEATURES
Wide V
CC
operation voltage : 2.4V ~ 5.5V
Very low power consumption :
Operation current : 31mA (Max.) at 55ns
V
CC
= 3.0V
2mA (Max.) at 1MHz
O
Standby current : 4/8uA (Max.) at 70/85 C
Operation current : 76mA (Max.) at 55ns
V
CC
= 5.0V
10mA (Max.) at 1MHz
O
Standby current : 25/50uA (Max.) at 70/85 C
High speed access time :
-55
55ns (Max.) at V
CC
: 3.0~5.5V
-70
70ns (Max.) at V
CC
: 2.7~5.5V
Automatic power down when chip is deselected
Easy expansion with CE1, CE2 and OE options
Three state outputs and TTL compatible
Fully static operation
Data retention supply voltage as low as 1.5V
DESCRIPTION
The BS62LV8001 is a high performance, very low power CMOS
Static Random Access Memory organized as 1,048,576 by 8 bits
and operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with maximum CMOS standby
current of 8/50uA at Vcc=3/5V at 85 C and maximum access time of
55/70ns.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2), and active LOW output
enable (OE) and three-state output drivers.
The BS62LV8001 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS62LV8001 is available in DICE form, JEDEC standard 44-pin
TSOP II and 48-ball BGA package.
O
POWER CONSUMPTION
POWER DISSIPATION
PRODUCT
FAMILY
BS62LV8001DC
BS62LV8001EC
BS62LV8001FC
BS62LV8001EI
BS62LV8001FI
Industrial
O
-40 C to +85 C
O
OPERATING
TEMPERATURE
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PKG TYPE
V
CC
=3.0V
10MHz
f
Max.
V
CC
=5.0V
V
CC
=3.0V
1MHz
V
CC
=5.0V
10MHz
f
Max.
1MHz
DICE
Commercial
O
O
+0 C to +70 C
25uA
4.0uA
9mA
39mA
75mA
1.5mA
19mA
30mA
TSOP II-44
BGA-48-0912
50uA
8.0uA
10mA
40mA
76mA
2mA
20mA
31mA
TSOP II-44
BGA-48-0912
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE1
NC
NC
DQ0
DQ1
VCC
VSS
DQ2
DQ3
NC
NC
WE
A19
A18
A17
A16
A15
1
A
B
C
D
E
F
G
H
NC
NC
DQ0
VSS
VCC
DQ3
NC
A18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
2
OE
NC
NC
DQ1
DQ2
NC
NC
A8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
5
A2
CE1
NC
DQ5
DQ6
NC
WE
A11
6
CE2
NC
DQ4
VCC
VSS
DQ7
NC
A19
A5
A6
A7
OE
CE2
A8
NC
NC
DQ7
DQ6
VSS
VCC
DQ5
DQ4
NC
NC
A9
A10
A11
A12
A13
A14
BLOCK DIAGRAM
A13
A17
A15
A18
A16
A14
A12
A7
A6
A5
A4
Address
Input
Buffer
22
Row
Decoder
2048
Memory Array
BS62LV8001EC
BS62LV8001EI
2048 x 4096
4096
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE1
CE2
WE
OE
V
CC
V
SS
8
Data
Output
Buffer
8
512
Column Decoder
18
Control
Address Input Buffer
8
Data
Input
Buffer
8
Column I/O
Write Driver
Sense Amp
3
A0
A3
A5
A17
NC
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
A11 A9 A8 A3 A2 A1 A0 A10 A19
48-ball BGA top view
Brilliance Semiconductor, Inc.
reserves the right to change products and specifications without notice.
R0201-BS62LV8001
1
Revision
2.4
Oct.
2008
BS62LV8001
PIN DESCRIPTIONS
Name
A0-A19 Address Input
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
WE Write Enable Input
Function
These 20 address inputs select one of the 1,048,576 x 8-bit in the RAM
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read form or write to the device. If either chip enable is not active, the device is
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
DQ0-DQ7 Data Input/Output
Ports
V
CC
V
SS
There 8 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
TRUTH TABLE
MODE
Not selected
(Power Down)
Output Disabled
Read
Write
CE1
H
X
L
L
L
CE2
X
L
H
H
H
WE
X
X
H
H
L
OE
X
X
H
L
X
I/O OPERATION
High Z
High Z
D
OUT
D
IN
V
CC
CURRENT
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
OPERATING RANGE
UNITS
V
O
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
RATING
-0.5
(2)
RANG
Commercial
Industrial
AMBIENT
TEMPERATURE
0 C to + 70 C
-40 C to + 85 C
O
O
O
O
V
CC
2.4V ~ 5.5V
2.4V ~ 5.5V
to 7.0
-40 to +125
-60 to +150
1.0
20
C
C
O
W
mA
CAPACITANCE
(1)
(T
A
= 25
O
C, f = 1.0MHz)
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
C
IN
C
IO
Input
Capacitance
Input/Output
Capacitance
V
IN
= 0V
V
I/O
= 0V
6
8
pF
pF
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. –2.0V in case of AC pulse width less than 30 ns.
R0201-BS62LV8001
1. This parameter is guaranteed and not 100% tested.
2
Revision
2.4
Oct.
2008
BS62LV8001
DC ELECTRICAL CHARACTERISTICS (T
A
=-40
O
C to +85
O
C)
PARAMETER
NAME
V
CC
V
IL
V
IH
I
IL
I
LO
V
OL
V
OH
I
CC
(5)
I
CC1
I
CCSB
I
CCSB1
(6)
PARAMETER
Power Supply
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Operating Power Supply
Current
Operating Power Supply
Current
Standby Current – TTL
Standby Current – CMOS
O
TEST CONDITIONS
MIN.
2.4
-0.5
(2)
TYP.
(1)
--
--
--
--
--
--
--
--
--
--
0.8
3.5
MAX.
5.5
0.8
V
CC
+0.3
1
1
0.4
--
31
76
2
10
1.0
2.0
8.0
50
(3)
UNITS
V
V
V
uA
uA
V
V
mA
mA
mA
uA
2.2
V
IN
= 0V to V
CC
V
I/O
= 0V to V
CC
,
CE1= V
IH
or CE2= V
IL
, or OE = V
IH
V
CC
= Max, I
OL
= 2.0mA
V
CC
= Min, I
OH
= -1.0mA
CE1 = V
IL
and CE2 = V
IH
,
I
DQ
= 0mA, f = F
MAX
(4)
--
--
--
2.4
V
CC
=3.0V
V
CC
=5.0V
V
CC
=3.0V
V
CC
=5.0V
V
CC
=3.0V
V
CC
=5.0V
V
CC
=3.0V
V
CC
=5.0V
--
--
--
--
CE1 = V
IL
and CE2 = V
IH
,
I
DQ
= 0mA, f = 1MHz
CE1 = V
IH
, or CE2 = V
IL
,
I
DQ
= 0mA
CE1≧V
CC
-0.2V or CE2≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
1. Typical characteristics are at T
A
=25 C and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: V
CC
+1.0V in case of pulse width less than 20 ns.
4. F
MAX
=1/t
RC.
O
5. I
CC (MAX.)
is 30mA/75mA at V
CC
=3.0V/5.0V and T
A
=70 C.
O
6. I
CCSB1(MAX.)
is 4.0uA/25uA at V
CC
=3.0V/5.0V and T
A
=70 C.
DATA RETENTION CHARACTERISTICS (T
A
= -40
O
C to +85
O
C)
SYMBOL
V
DR
I
CCDR
(3)
t
CDR
t
R
PARAMETER
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
O
TEST CONDITIONS
CE1≧V
CC
-0.2V or CE2≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
CE1≧V
CC
-0.2V or CE2≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
MIN.
1.5
--
0
TYP.
(1)
--
0.4
--
MAX.
--
4.0
--
--
UNITS
V
uA
ns
ns
See Retention Waveform
t
RC
(2)
--
1. V
CC
=1.5V, T
A
=25 C and not 100% tested.
2. t
RC
= Read Cycle Time.
O
3. I
CCRD(Max.)
is 2.0uA at T
A
=70 C.
LOW V
CC
DATA RETENTION WAVEFORM (1) (CE1 Controlled)
Data Retention Mode
V
CC
V
CC
V
DR
≧1.5V
V
CC
t
CDR
V
IH
CE1≧V
CC
- 0.2V
t
R
V
IH
CE1
R0201-BS62LV8001
3
Revision
2.4
Oct.
2008
BS62LV8001
LOW V
CC
DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
V
CC
V
DR
≧1.5V
V
CC
V
CC
t
CDR
CE2≦0.2V
t
R
CE2
V
IL
V
IL
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Reference Level
Output Load
t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
Others
Vcc / 0V
1V/ns
0.5Vcc
C
L
= 5pF+1TTL
C
L
= 30pF+1TTL
ALL INPUT PULSES
1 TTL
Output
C
(1)
L
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM “H” TO “L”
MAY CHANGE
FROM “L” TO “H”
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “L” TO “H”
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
V
CC
GND
10%
90%
90%
10%
→ ←
Rise Time :
1V/ns
→ ←
Fall Time :
1V/ns
1. Including jig and scope capacitance.
AC ELECTRICAL CHARACTERISTICS (T
A
= -40
O
C to +85
O
C)
READ CYCLE
JEDEC
PARANETER
PARAMETER
NAME
NAME
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Output Enable to Output Low Z
Chip Select to Output High Z
Chip Select to Output High Z
Output Enable to Output High Z
Data Hold from Address Change
(CE1)
(CE2)
(CE1)
(CE2)
(CE1)
(CE2)
CYCLE TIME : 55ns
(V
CC
= 3.0~5.5V)
MIN. TYP. MAX.
55
--
--
--
--
10
10
10
--
--
--
10
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
55
25
--
--
--
30
30
25
--
CYCLE TIME : 70ns
(V
CC
= 2.7~5.5V)
MIN. TYP. MAX.
70
--
--
--
--
10
10
10
--
--
--
10
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
70
30
--
--
--
35
35
30
--
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AVAX
t
AVQX
t
E1LQV
t
E2HQV
t
GLQV
t
E1LQX
t
E2HQX
t
GLQX
t
E1HQZ
t
E2LQZ
t
GHQZ
t
AVQX
t
RC
t
AA
t
ACS1
t
ACS2
t
OE
t
CLZ1
t
CLZ2
t
OLZ
t
CHZ1
t
CHZ2
t
OHZ
t
OH
R0201-BS62LV8001
4
Revision
2.4
Oct.
2008
BS62LV8001
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1
(1,2,4)
t
RC
ADDRESS
t
OH
D
OUT
t
AA
t
OH
READ CYCLE 2
(1,3,4)
CE1
t
ACS1
CE2
t
CLZ
(5)
t
ACS2
t
CHZ1
, t
CHZ2
(5)
D
OUT
READ CYCLE 3
(1, 4)
t
RC
ADDRESS
t
AA
OE
t
OE
CE1
t
CLZ1
(5)
CE2
t
CLZ2
(5)
D
OUT
t
OLZ
t
ACS1
t
CHZ1
(1,5)
t
OHZ
(5)
t
OH
t
ACS2
t
CHZ2
(1,5)
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = V
IL
and CE2= V
IH
.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = V
IL
.
5. Transition is measured
±
500mV from steady state with C
L
= 5pF.
The parameter is guaranteed but not 100% tested.
R0201-BS62LV8001
5
Revision
2.4
Oct.
2008
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