BSI
FEATURES
Very Low Power/Voltage CMOS SRAM
128K X 16 bit
BS616LV2017
• Vcc operation voltage : 4.5V ~ 5.5V
• Very low power consumption :
Vcc = 5.0V C-grade: 60mA (@55ns) operating current
I -grade: 62mA (@55ns) operating current
C-grade: 53mA (@70ns) operating current
I -grade: 55mA (@70ns) operating current
1.0uA(Typ.) CMOS standby current
• High speed access time :
-55
55ns
-70
70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
DESCRIPTION
The BS616LV2017 is a high performance , very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
1.0uA at 5.0V /25
o
C and maximum access time of 55ns at 5.0V / 85
o
C.
Easy memory expansion is provided by active LOW chip enable (CE),
active LOW output enable(OE) and three-state output drivers.
The BS616LV2017 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV2017 is available in DICE form , JEDEC standard 44-pin
TSOP Type II package and 48-ball BGA package.
PRODUCT FAMILY
PRODUCT
FAMILY
BS616LV2017DC
BS616LV2017EC
BS616LV2017AC
BS616LV2017DI
BS616LV2017EI
BS616LV2017AI
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
( ns )
55ns: 4.5~5.5V
70ns: 4.5~5.5V
( I
CCSB1
, Max )
Vcc=5.0V
POWER DISSIPATION
STANDBY
Operating
( I
CC
, Max )
Vcc=5.0V
55ns
70ns
PKG TYPE
DICE
TSOP2-44
BGA-48-0608
DICE
TSOP2-44
BGA-48-0608
+0
O
C to +70
O
C
4.5V ~5.5V
55/70
10uA
60mA
53mA
-40
O
C to +85
O
C
4.5V ~ 5.5V
55/70
30uA
62mA
55mA
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC
BLOCK DIAGRAM
A8
A13
A15
A16
A14
A12
A7
A6
A5
A4
Address
Input
Buffer
20
Row
Decoder
1024
Memory Array
1024 x 2048
BS616LV2017EC
BS616LV2017EI
2048
DQ0
16
Data
Input
Buffer
16
Column I/O
1
A
B
C
D
E
F
G
H
LB
D8
D9
VSS
VCC
D14
D15
N.C.
2
OE
UB
D10
D11
D12
D13
N.C.
A8
3
A0
A3
A5
N.C.
N.C.
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE
D1
D3
D4
D5
WE
A11
6
N.C.
D0
D2
VCC
VSS
D6
D7
N.C.
.
.
.
.
DQ15
.
.
.
.
Write Driver
Sense Amp
128
Column Decoder
16
Data
Output
16
Buffer
CE
WE
OE
UB
LB
Vcc
Gnd
Control
14
Address Input Buffer
A11 A9 A3 A2 A1 A0 A10
Brilliance Semiconductor, Inc
.
reserves the right to modify document contents without notice.
R0201-BS616LV2017
1
Revision 1.1
Jan.
2004
BSI
PIN DESCRIPTIONS
BS616LV2017
Name
A0-A16 Address Input
CE Chip Enable Input
Function
These 17 address inputs select one of the 131,072 x 16-bit words in the RAM.
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
DQ0 - DQ15 Data Input/Output
Ports
Vcc
Gnd
Lower byte and upper byte data input/output control pins.
These 16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
TRUTH TABLE
MODE
Not selected
(Power Down)
Output Disabled
CE
H
X
L
L
L
WE
X
X
X
H
H
OE
X
X
X
H
L
LB
X
H
H
X
L
Read
H
L
L
Write
L
L
X
H
L
UB
X
H
H
X
L
L
H
L
L
H
D0~D7
High Z
High Z
High Z
High Z
Dout
High Z
Dout
Din
X
Din
D8~D15
High Z
High Z
High Z
High Z
Dout
Dout
High Z
Din
Din
X
Vcc CURRENT
I
CCSB
, I
CCSB1
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
R0201-BS616LV2017
2
Revision 1.1
Jan.
2004
BSI
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
BS616LV2017
OPERATING RANGE
UNITS
V
O
RATING
-0.5 to
Vcc+0.5
-40 to +85
-60 to +150
1.0
20
RANGE
Commercial
Industrial
AMBIENT
TEMPERATURE
0
O
C to +70
O
C
-40
O
C to +85
O
C
Vcc
4.5V ~ 5.5V
4.5V ~ 5.5V
C
C
O
W
mA
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
C
IN
C
DQ
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
MAX.
UNIT
V
IN
=0V
V
I/O
=0V
6
8
pF
pF
1. This parameter is guaranteed and not 100% tested.
DC ELECTRICAL CHARACTERISTICS
( TA = -40 to + 85
o
C )
PARAMETER
NAME
V
IL
V
IH
I
IL
I
LO
V
OL
V
OH
I
CC
(5)
PARAMETER
Guaranteed Input Low
(2)
Voltage
Guaranteed Input High
(2)
Voltage
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Operating Power Supply
Current
Standby Current-TTL
TEST CONDITIONS
Vcc =5.0V
Vcc =5.0V
Vcc = Max, V
IN
= 0V to Vcc
Vcc = Max,CE = V
IH
or OE = V
IH
,
V
I/O
= 0V to Vcc
Vcc = Max, I
OL
= 2.0mA
Vcc = Min, I
OH
= -1.0mA
CE = V
IL
,
I
DQ
= 0mA, F = Fmax
(3)
CE=V
IH
I
DQ
= 0mA
CE
≧
V
cc
-0.2
V
,
V
IN
≧V
cc
-0.2
V
or
V
IN
≦0.2
V
Vcc =5.0V
Vcc =5.0V
V
cc
=5.0V
70ns
55ns
MIN.
-0.5
2.2
--
--
--
2.4
--
TYP.
(1)
MAX.
--
--
--
--
--
--
--
0.8
V
cc
+0.3
1
1
0.4
--
55
62
1.0
UNITS
V
V
uA
uA
V
V
mA
I
CCSB
I
CCSB1
(4)
Vcc =5.0V
--
--
mA
Standby Current-CMOS
Vcc =5.0V
--
1.0
30
uA
1.
Typical characteristics are at T
A
= 25
o
C.
2.
These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
4.I
ccs
B1_Max.
is 10uA at Vcc=5.0V and T
A
=70
o
C.
3.
Fmax = 1/t
RC
.
o
C.
5.
Icc
_Max.
is 60mA(@55ns) / 53mA(@70ns) at Vcc=5.0 and T
A
=0~70
DATA RETENTION CHARACTERISTICS
( TA = -40 to + 85
o
C )
SYMBOL
V
DR
I
CCDR
t
CDR
t
R
(3)
PARAMETER
Vcc for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
TEST CONDITIONS
CE
≧
Vcc - 0.2V,
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
CE
≧
Vcc - 0.2V,
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
See Retention Waveform
MIN.
1.5
--
0
T
RC (2)
TYP.
(1)
--
0.1
--
--
MAX.
--
1.0
--
--
UNITS
V
uA
ns
ns
1.
Vcc = 1.5V, T
A
= + 25
O
C
3.
Icc
DR_MAX.
is 0.7uA at T
A
=70
o
C.
R0201-BS616LV2017
2.
t
RC
= Read Cycle Time
3
Revision 1.1
Jan.
2004
BSI
LOW V
CC
DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
BS616LV2017
V
DR
≥
1.5V
Vcc
V
IH
Vcc
Vcc
t
CDR
CE
≥
Vcc - 0.2V
t
R
V
IH
CE
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
KEY TO SWITCHING WAVEFORMS
Vcc / 0V
1V/ns
0.5Vcc
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Output Load
C
L
= 100pF+1TTL
C
L
= 30pF+1TTL
,
AC ELECTRICAL CHARACTERISTICS
( TA = -40 to + 85
o
C )
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
Data Hold from Address Change
CYCLE TIME : 55ns
(Vcc = 4.5~5.5V)
CYCLE TIME : 70ns
(Vcc = 4.5~5.5V)
MIN. TYP. MAX.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN. TYP. MAX.
t
AVAX
t
AVQV
t
ELQV
t
BA
t
GLQV
t
E1LQX
t
BE
t
GLQX
t
EHQZ
t
BDO
t
GHQZ
t
AXOX
t
RC
t
AA
t
ACS
t
BA
(1)
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
55
--
(CE)
(LB,UB)
(CE)
(LB,UB)
(CE)
(LB,UB)
--
--
--
10
10
5
--
--
--
10
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
30
30
--
--
--
30
30
25
--
70
--
--
--
--
10
10
5
--
--
--
10
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
35
35
--
--
--
35
35
30
--
NOTE :
1. t
BA
is 30ns/35ns (@speed=55ns/70ns) with address toggle. ; t
BA
is 55ns/70ns (@speed=55ns/70ns) without address toggle.
R0201-BS616LV2017
4
Revision 1.1
Jan.
2004
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
BS616LV2017
t
RC
ADDRESS
t
D
OUT
t
OH
AA
t
OH
READ CYCLE2
(1,3,4)
CE
t
ACS
t
BA
LB,UB
t
BE
D
OUT
t
(5)
CLZ
t
BDO
t
CHZ
(5)
READ CYCLE3
(1,4)
t
RC
ADDRESS
t
OE
AA
t
OE
CE
t
OH
t
OLZ
t
(5)
CLZ
t
ACS
t
OHZ
(5)
(1,5)
t
CHZ
t
BA
LB,UB
t
BE
D
OUT
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE = V
IL
.
3. Address valid prior to or coincident with CE transition low.
4. OE = V
IL
.
5. The parameter is guaranteed but not 100% tested.
t
BDO
R0201-BS616LV2017
5
Revision 1.1
Jan.
2004
Embedded System
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