CorePCI v5.41
Product Summary
Intended Use
•
Most Flexible High-Performance PCI Offering
–
Target, Master, and Master/Target, which
includes Target+DMA and Target+Master
functions
33 MHz or 66 MHz Performance
32-Bit or 64-Bit PCI Bus Widths
Memory, I/O, and Configuration Support
Synthesis and Simulation Support
•
•
Synthesis: Exemplar
TM
, Synopsys
®
DC / FPGA Compiler
TM
,
and Synplicity
®
Simulation: Vital-Compliant VHDL Simulators and
OVI- Compliant Verilog Simulators
Macro Verification and Compliance
•
•
•
•
Actel-Developed Testbench
Hardware Tested
I/O Drive Compliant in Targeted Devices
Compliant with the PCI 2.3 Specification
–
–
–
•
Backend Support for Synchronous DRAM, SRAM,
and I/O Subsystems
Version
Key Features
•
•
•
•
•
Two User-Configurable Base Address Registers for
Target Functions
Interrupt Capability
Built-in DMA Controller in all Master Functions
Flexible Backend Data Flow Control
Hot-Swap Extended
Compact PCI
Capabilities
Support
for
General Description ................................................... 2
CorePCI Device Requirements ................................... 3
Utilization Statistics ................................................... 5
CorePCI IP Functional Block Diagram ....................... 6
Data Transactions ....................................................... 6
I/O Signal Descriptions ............................................... 6
CorePCI Target Function .......................................... 12
CorePCI Master Function ......................................... 17
Master Register Access ............................................. 19
System Timing .......................................................... 22
PCI Target Transactions ............................................ 22
PCI Master Transactions ........................................... 35
Backend Control of DMA Activity ........................... 38
Ordering Information .............................................. 40
List of Changes ......................................................... 41
Datasheet Categories ............................................... 41
This datasheet defines the functionality of Version 5.41
for CorePCI.
Contents
Data Transfer Rates
•
•
Fully Compliant Zero-Wait-State Burst (32-Bit or
64-Bit Transfer Each Cycle)
Optional Paced Burst
Between Transfers)
(Wait
States
Inserted
Supported Families
•
•
•
•
•
•
•
ProASIC3/E
ProASIC
PLUS 1
Axcelerator
RTAX-S
SX
SX-A
RTSX-S
1
Design Source Provided
•
•
VHDL and Verilog-HDL Design Source
Actel-Developed Testbench
October 2004
© 2004 Actel Corporation
v 4 .0
1
CorePCI v5.41
General Description
CorePCI connects I/O, memory, and processor subsystem
resources to the main system via the PCI bus. CorePCI is
intended for use with a wide variety of peripherals
where high-performance data transactions are required.
Figure 1 on page 2
depicts typical system applications
using the baseline IP core. While CorePCI can handle any
transfer rate, most applications will operate at zero wait
states. When required, wait states can automatically be
inserted by a slower peripheral.
The core consists of up to four basic units: the Target
controller, the Master controller, the backend, and the
FRAMEn
REQ64n
IRDYn
DEVSELn
ACK64n
TRDYn
SERRn
IDSEL
AD
PAR
PAR64
CBE
PERRn
INTAn
REQn
GNTn
CLK
RSTn
STOPn
wrapper. Both the Target and Master controllers remain
constant for a variety of backends. A backend controller
provides the necessary control for the I/O or memory
subsystem and interfaces to the Target controller
through a generic interface. The wrapper combines the
Target and Master blocks with the backend for
implementation in a single Actel device.
CorePCI can be customized in two different ways. First, a
variety of variables are provided to easily change
parameters such as memory and I/O sizes. The second
method is to develop user-specific backend controllers
for non-standard peripherals.
Master Control Signals
Backend
Controller
System CPU
Memory Control Signals
MEM_ADDRESS BUS
Memory
Subsystem
Sync SRAM
Sync DRAM
MEM_DATA BUS
BAR1_ENABLE
CorePCI
Target+Master
Controller
Optional
Memory or I/O
Subsystem
PCI Bus
Master
Bridge
Target
Figure 1 •
CorePCI System Block Diagram
2
v4.0
CorePCI v5.41
CorePCI Device Requirements
Performance requirements and bus size both drive device
selection.
Table 1
summarizes the device requirements. A
typical 64-bit PCI system requires at least 200 I/Os.
Table 4
on page 5
shows typical pin counts. The actual number
of I/O pins depends on the user backend interface. The
table assumes the complete backend interface is
connected to I/O pins rather than internal logic. Some
applications such as PCI-UART target could only require
one backend I/O pin.
Table 1
and
Table 2 on page 4
are
Table 1 •
Supported Devices
Family
33 MHz 32-bit
SXA
RTSX-S
AX
RTAX-S
APA
ProASIC3/E
33 MHz 64-Bit
SXA
RTSX-S
AX
RTAX-S
APA
ProASIC3/E
66 MHz 32-Bit
SXA
RTSX-S
AX
RTAX-S
APA
ProASIC3/E
66 MHz 64-Bit
SXA
RTSX-S
AX
RTAX-S
APA
ProASIC3/E
Notes:
1. Required speed grades based on Libero design flows.
2. N/A indicates device not supported.
3. All packages are supported.
4. O/R indicates on request.
PCI Voltage
3.3 & 5.0
3.3 & 5.0
3.3
3.3
3.3
3.3
3.3 & 5.0
3.3 & 5.0
3.3
3.3
3.3
3.3
3.3 & 5.0
3.3 & 5.0
3.3
3.3
3.3
3.3
3.3 & 5.0
3.3 & 5.0
3.3
3.3
3.3
3.3
Smallest Device
A54SX16A
RT54SX32S
AX125
RTAX250S
APA075
A3P125
A54SX16A
RT54SX32S
AX125
RTAX 250S
APA075
A3P125
A54SX16A
RT54SX32S
AX125
RTAX1000S
APA075
A3P125
A54SX16A
RT54SX32S
AX125
RTAX1000S
APA075
A3P125
Commercial
STD
–1
STD
STD
STD
STD
STD
N/A
STD
–1
N/A
STD
–3
N/A
–1
N/A
N/A
-2
–3
N/A
–1
N/A
N/A
-2
Industrial
STD
–1
STD
–1
STD
STD
STD
N/A
STD
–1
N/A
STD
–3
N/A
–1
N/A
N/A
-2
–3
N/A
–1
N/A
N/A
-2
Military
STD
–1
STD
–1
STD
STD
STD
N/A
STD
–1
N/A
STD
N/A
N/A
O/R
O/R
N/A
N/A
N/A
N/A
O/R
O/R
N/A
N/A
summaries of the minimum device requirements for
various PCI size/performance options. In order to meet
the PCI timing requirements for output valid (6 ns for 66
MHz, 11 ns for 33 MHz) and input setup (3 ns for 66 MHz,
7 ns for 33 MHz) times, the speed grades shown in
Table 1
must be used. The RTSX-S, ProASIC, and
ProASIC
PLUS
families should only be employed for 32-bit/
33 MHz PCI applications.
v4.0
3
CorePCI v5.41
Table 2 •
Device Utilization for CorePCI Functions
Target
Device
A54SX16A
A54SX16P
A54SX32A
A54SX72A
RT54SX32S
RT54SX72S
AX125
AX250
AX500
AX1000
AX2000
RTAX250S
RTAX1000S
RTAX2000S
APA075
APA150
APA300
APA450
APA600
APA750
APA1000
A3P125
A3P250
A3P400
A3P600
A3P1000
A3PE600
A3PE1500
A3PE3000
Notes:
1. Refers to the SX, SX-A, RTSX, and RTSXS families.
2. N/A indicates either insufficient I/O resources, or the device does not support 66 MHz operation.
3.
Table 3 on page 5
gives more detailed utilization data.
4. Utilization will vary depending on core configuration, table shows typical values.
5. All packages are supported for the devices listed above.
32-Bit
54%
54%
27%
13%
27%
13%
39%
19%
10%
4%
2%
19%
4%
2%
40%
20%
15%
10%
6%
4%
2%
45%
22%
15%
10%
5%
10%
3%
2%
64-Bit
N/A
N/A
32%
15%
32%
15%
45%
22%
11%
5%
3%
11%
5%
3%
N/A
N/A
N/A
N/A
N/A
N/A
N/A
49%
25%
17%
11%
6%
11%
4%
2%
Master
32-Bit
89%
89%
45%
21%
45%
21%
64%
31%
16%
7%
4%
16%
7%
4%
62%
31%
23%
16%
9%
6%
3%
72%
36%
24%
16%
9%
16%
6%
3%
64-Bit
N/A
N/A
56%
27%
27%
27%
79%
38%
20%
9%
5%
20%
9%
5%
N/A
N/A
N/A
N/A
N/A
N/A
N/A
90%
45%
36%
20%
11%
20%
7%
4%
Target+DMA
32-Bit
86%
86%
43%
21%
43%
21%
62%
30%
16%
7%
4%
16%
7%
4%
62%
31%
23%
16%
9%
6%
3%
72%
36%
24%
16%
9%
16%
6%
3%
64-Bit
N/A
N/A
57%
27%
57%
27%
81%
39%
20%
9%
5%
20%
9%
5%
N/A
N/A
N/A
N/A
N/A
N/A
N/A
90%
45%
36%
20%
11%
20%
7%
4%
Target+Master
32-Bit
94%
94%
48%
23%
48%
23%
68%
32%
17%
8%
4%
17%
8%
4%
80%
40%
30%
20%
11%
7%
4%
76%
36%
26%
17%
10%
17%
6%
3%
64-Bit
N/A
N/A
56%
27%
56%
27%
80%
38%
20%
9%
5%
20%
9%
5%
N/A
N/A
N/A
N/A
N/A
N/A
N/A
90%
45%
36%
20%
11%
20%
20%
4%
4
v4.0
CorePCI v5.41
Utilization Statistics
Utilization statistics are given in
Table 2 on page 4.
Table 3
gives a detailed breakdown of the actual gate
counts for each of the core variations and options listed
in
Table 3.
The antifuse column indicates the typical R
and C module counts for the SX, SX-A, RTSX-S, and
Axcelerator families. The Flash column indicates the tile
Table 3 •
Utilization Statistics for CorePCI
Antifuse
Function
32-Bit Target Controller
64-Bit Target Controller
32-Bit Master Controller
64-Bit Master Controller
32-Bit Target+DMA Controller
64-Bit Target+DMA Controller
32-Bit Target/Master Controller
64-Bit Target/Master Controller
SDRAM Controller
BAR #1 Support
DMA Mapped into I/O
3
Notes:
1. The sequential number is the R-module usage and the combinatorial number is the C-module usage.
2. Total number of tiles required.
3. Only applicable to Target+DMA functions.
Table 4 •
Core I/O Requirements
I/O Count
Backend
Core
32-Bit Target Controller
64-Bit Target Controller
32-Bit Master Controller
64-Bit Master Controller
32-Bit Target+DMA Controller
64-Bit Target+DMA Controller
32-Bit Target+Master Controller
64-Bit Target+Master Controller
PCI
48
87
50
89
50
89
50
89
Minimum
1
1
1
1
1
1
1
1
Standard*
74
113
83
122
74
113
83
122
Total
Minimum
49
88
51
90
51
90
51
90
Standard*
122
200
133
211
124
202
133
211
Sequential
262
350
480
600
400
554
470
570
70
30
30
1
counts for the ProASIC
PLUS
and ProASIC3/E families.
These are typical numbers and will vary based on the
synthesis tools and constraints used. Each backend
requires different amounts of logic depending on the
complexity of the controller. An SDRAM controller is
included as an example.
ProASIC
PLUS
Flash
2
Total
790
910
1290
1600
1250
1641
1370
1620
200
100
120
Tiles
1218
N/A
1900
N/A
1904
N/A
2437
N/A
230
140
120
ProASIC3/E
Flash
2
Tiles
1194
1266
1862
2590
1866
2815
2389
2720
225
137
117
Combinatorial
528
560
810
1000
850
1087
900
1050
130
70
90
Note:
*Assumes all the backend I/O pins as listed in the data sheet are connected to I/O pins rather than to internal FPGA logic.
v4.0
5
京公网安备 11010802033920号
EEWORLD
