Data Sheet
August 1996
ORCA
™
OR2CxxA (5.0 V) and OR2TxxA (3.3 V) Series
Field-Programmable Gate Arrays
Features
s
s
Flip-flop/latch options to allow programmable prior-
ity of synchronous set/reset vs. clock enable
Enhanced cascadable nibble-wide data path
capabilities for comparators and multiplexers
Innovative, abundant, and hierarchical nibble-
oriented routing resources that allow automatic
use of internal gates for all device densities without
sacrificing performance
Internal fast-carry for arithmetic functions
Upward bit stream compatible from the
ORCA
ATT2Cxx/ATT2Txx series of devices
TTL or CMOS input levels programmable per pin
for the OR2CxxA (5.0 V) devices
Individually programmable drive capability: 12 mA
sink/6 mA source or 6 mA sink/3 mA source
Built-in boundary scan (
IEEE
*1149.1)
Full PCI bus compliance
Supported by industry-standard CAE tools for
design entry, synthesis, and simulation with
ORCA
Foundry Development System support (for back-
end implementation)
High-performance, cost-effective, low-power
0.35
µm
CMOS technology (four-input look-up
table delay less than 2.1 ns with -4 speed grade,
less than 1.7 ns with advance -5 speed grade)
High density (up to 43,200 usable, logic-only
gates; or 99,400 gates including RAM)
Up to 480 user I/Os (OR2TxxA I/Os are 5 V
tolerant to allow interconnection to both 3.3 V and
5 V devices, selectable on a per-pin basis)
Four 16-bit look-up tables and four latches/flip-
flops per PFU, nibble-oriented for implementing
4-, 8-, 16-, and/or 32-bit (or wider) bus structures
Fast on-chip user SRAM has features to simplify
RAM design and increase RAM speed:
— Asynchronous single port: 64 bits/PFU
— Synchronous single port: 64 bits/PFU
— Synchronous dual port: 32 bits/PFU
Improved ability to combine PFUs to create larger
RAM structures using write-port enable
Fast, dense multipliers can be created with the
multiplier mode (4 x 1 multiplier/PFU):
— 8 x 8 multiplier requires only 16 PFUs
— 30% increase in speed
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
*
IEEE
is a registered trademark of The Institute of Electrical and
Electronics Engineers.
Table 1.
ORCA
OR2CxxA/OR2TxxA Series FPGAs
Device
OR2C04A/OR2T04A
OR2C06A/OR2T06A
OR2C08A/OR2T08A
OR2C10A/OR2T10A
OR2C12A/OR2T12A
OR2C15A/OR2T15A
OR2C26A/OR2T26A
OR2C40A/OR2T40A
Usable
Gates*
4,800—11,000
6,900—15,900
9,400—21,600
12,300—28,300
15,600—35,800
19,200—44,200
27,600—63,600
43,200—99,400
Latches/FFs
400
576
784
1024
1296
1600
2304
3600
Max User
RAM Bits
6,400
9,216
12,544
16,384
20,736
25,600
36,864
57,600
User
I/Os
160
192
224
256
288
320
384
480
Array Size
10 x 10
12 x 12
14 x 14
16 x 16
18 x 18
20 x 20
24 x 24
30 x 30
* The first number in the usable gates column assumes 48 gates per PFU (12 gates per 4-input LUT/FF pair) for logic-only designs. The
second number assumes 30% of a design is RAM. PFUs used as RAM are counted at 4 gates per bit, with each PFU capable of imple-
menting a 16 x 4 RAM (or 256 gates) per PFU.
ORCA
OR2CxxA and OR2TxxA Series FPGAs
Data Sheet
August 1996
Table of Contents
Contents
Page
Contents
Page
Features ..................................................................... 1
Description ................................................................. 3
ORCA
Foundry Development
System Overview ................................................. 4
Architecture ................................................................ 5
Programmable Logic Cells ......................................... 5
Programmable Function Unit .................................. 5
Look-Up Table Operating Modes ............................ 7
Latches/Flip-Flops ................................................ 15
PLC Routing Resources ....................................... 17
PLC Architectural Description ............................... 22
Programmable Input/Output Cells ............................ 25
Inputs .................................................................... 25
Outputs ................................................................. 26
PIC Routing Resources ........................................ 27
PIC Architectural Description ................................ 29
PLC-PIC Routing Resources ................................ 31
Interquad Routing ..................................................... 32
Subquad Routing .................................................. 34
PIC Interquad (MID) Routing ................................ 36
Programmable Corner Cells ..................................... 37
Programmable Routing ......................................... 37
Special-Purpose Functions ................................... 37
Clock Distribution Network ....................................... 37
Primary Clock ....................................................... 37
Secondary Clock .................................................. 38
Selecting Clock Input Pins .................................... 39
FPGA States of Operation ........................................ 40
Initialization ........................................................... 40
Configuration ........................................................ 41
Start-Up ................................................................ 41
Reconfiguration .................................................... 42
Partial Reconfiguration ......................................... 42
Other Configuration Options .................................. 42
Configuration Data Format ....................................... 42
Using
ORCA
Foundry to Generate
Configuration RAM Data..................................... 43
Configuration Data Frame .................................... 43
Bit Stream Error Checking ........................................ 46
FPGA Configuration Modes ......................................46
Master Parallel Mode ............................................46
Master Serial Mode ...............................................47
Asynchronous Peripheral Mode ............................48
Synchronous Peripheral Mode ..............................48
Slave Serial Mode .................................................49
Slave Parallel Mode ..............................................49
Daisy Chain ..........................................................50
Readback ................................................................. 51
Boundary Scan .........................................................52
Boundary-Scan Instructions .................................53
ORCA
Boundary-Scan Circuitry ...........................54
ORCA
Timing Characteristics ...................................58
Estimating Power Dissipation .................................. 60
Pin Information ......................................................... 64
Package Compatibility ..........................................66
Package Thermal Characteristics ...........................130
Package Coplanarity ...............................................131
Package Parasitics .................................................131
Absolute Maximum Ratings ....................................133
Recommended Operating Conditions .................... 133
Electrical Characteristics ........................................ 134
Timing Characteristics ............................................135
Measurement Conditions ........................................161
Output Buffer Characteristics .................................162
Outline Diagrams ....................................................164
Terms and Definitions .........................................164
84-Pin PLCC .......................................................165
100-Pin TQFP ..................................................... 166
144-Pin TQFP ..................................................... 167
160-Pin QFP .......................................................168
208-Pin SQFP .....................................................169
208-Pin SQFP2 ...................................................170
240-Pin SQFP..................................................... 171
240-Pin SQFP2................................................... 172
256-Pin PBGA ....................................................173
304-Pin SQFP..................................................... 174
304-Pin SQFP2................................................... 175
352-Pin PBGA .................................................... 176
432-Pin EBGA .................................................... 177
600-Pin EBGA .................................................... 178
Ordering Information ...............................................179
2
Lucent Technologies Inc.
Data Sheet
August 1996
ORCA
OR2CxxA and OR2TxxA Series FPGAs
configuration RAM. All logic is done in the PFU. Each
PFU contains four 16-bit look-up tables (LUTs) and four
latches/flip-flops (FFs).
The PLC architecture provides a balanced mix of logic
and routing which allows a higher utilized gate/PFU
than alternative architectures. The routing resources
carry logic signals between PFUs and I/O pads. The
routing in the PLC is symmetrical about the horizontal
and vertical axes. This improves routability by allowing
a bus of signals to be routed into the PLC from any
direction.
Some examples of the resources required and the per-
formance that can be achieved using these devices are
represented in Table 2.
The FPGA’s functionality is determined by internal
configuration RAM. The FPGA’s internal initialization/
configuration circuitry loads the configuration data at
powerup or under system control. The RAM is loaded
by using one of several configuration modes. The con-
figuration data resides externally in an EEPROM,
EPROM, or ROM on the circuit board, or any other
storage media. Serial ROMs provide a simple, low pin
count method for configuring FPGAs.
Description
The
ORCA
OR2CxxA/OR2TxxA series of SRAM-
based FPGAs are an enhanced version of the
ORCA
2C/2T architecture. The latest
ORCA
series includes
patented architectural enhancements that make func-
tions faster and easier to design while conserving the
use of PLCs and routing resources.
The OR2CxxA/OR2TxxA devices can be used as drop-
in replacements for the ATT2Cxx/ATT2Txx series,
respectively, and they are also bit stream compatible
with each other. Both series of devices are imple-
mented using two 0.35
µm
processes: one is optimized
for 5.0 V operation, and the other is optimized for 3.3 V
operation to allow equivalent system speeds at less
than half the power. The usable gate counts associated
with each series are provided in Table 1. Both series
are offered in a variety of packages, speed grades, and
temperature ranges.
The
ORCA
series FPGA consists of two basic ele-
ments: programmable logic cells (PLCs) and program-
mable input/output cells (PICs). An array of PLCs is
surrounded by PICs as shown in Figure 1. Each PLC
contains a programmable function unit (PFU). The
PLCs and PICs also contain routing resources and
Table 2.
ORCA
OR2CxxA/OR2TxxA System Performance
Function
16-bit loadable up/down counter
16-bit accumulator
8 x 8 parallel multiplier:
— multiplier mode, unpipelined
1
— ROM mode, unpipelined
2
— multiplier mode, pipelined
3
32 x 16 RAM:
— single port (Read and Write/Cycle)
4
— single port
5
— dual port
6
36-bit parity check (internal)
32-bit address decode (internal)
1.
2.
3.
4.
Speed Grade
# PFUs
-2
4
4
22
36
44
9
9
16
4
3.25
51
51
14
21
57
21
31
39
13.9
12.3
-3
67
67
19
28
76
27
43
53
11.0
9.5
-4
87
87
24
34
96
34
65
84
9.1
7.5
-5
102
102
30
43
115
46
76
95
7.3
6.0
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
Implemented using 4 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
Implemented using a 256 x 8 ROM (unpipelined), register-to-register, one 8-bit input, one fixed operand, one 8-bit output.
Implemented using 4 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (28 of 44 PFUs contain only pipelining registers.
Implemented using 16 x 4 synchronous single-port RAM mode allowing both read and write per clock cycle, including write/read address
multiplexer.
5. Implemented using 16 x 4 synchronous single-port RAM mode allowing either read or write per clock cycle, including write/read address mul-
tiplexer.
6. Implemented using 16 x 2 synchronous dual-port RAM mode.
7. Shaded values are preliminary.
Lucent Technologies Inc.
3
ORCA
OR2CxxA and OR2TxxA Series FPGAs
Data Sheet
August 1996
Description
(continued)
VI
PT1
PL1
PT2
R1C2
PT3
R1C3
PT4
R1C4
PT5
R1C5
PT6
R1C6
PT7
R1C7
PT8
R1C8
PT9
R1C9
PT10
R1C10
TMID
PT11
PT12
PT13
PT14
PT15
PT16
PT17
PT18
PT19
PT20
PR1
R1C1
R1C11 R1C12 R1C13 R1C14 R1C15 R1C16 R1C17 R1C18 R1C19 R1C20
PL2
PR2
R2C1
R2C2
R2C3
R2C4
R2C5
R2C6
R2C7
R2C8
R2C9
R2C10
vIQ
R2C11 R2C12 R2C13 R2C14 R2C15 R2C16 R2C17 R2C18 R2C19 R2C20
PR3
PL3
R3C1
R3C2
R3C3
R3C4
R3C5
R3C6
R3C7
R3C8
R3C9
R3C10
R3C11 R3C12 R3C13 R3C14 R3C15 R13C16 R3C17 R3C18 R3C19 R3C20
PR4
PL4
R4C1
R4C2
R4C3
R4C4
R4C5
R4C6
R4C7
R4C8
R4C9
R4C10
R4C11 R4C12 R4C13 R4C14 R4C15 R4C16 R4C17 R4C18 R4C19 R4C20
PL5
PR5
R5C1
R5C2
R5C3
R5C4
R5C5
R5C6
R5C7
R5C8
R5C9
R5C10
R5C11 R5C12 R5C13 R5C14 R5C15 R5C16 R5C17 R5C18 R5C19 R5C20
PR6
PL6
R6C1
R6C2
R6C3
R6C4
R6C5
R6C6
R6C7
R6C8
R6C9
R6C10
R6C11 R6C12 R6C13 R6C14 R6C15 R6C16 R6C17 R6C18 R6C19 R6C20
PR7
PL7
R7C1
R7C2
R7C3
R7C4
R7C5
R7C6
R7C7
R7C8
R7C9
R7C10
R7C11 R7C12 R7C13 R7C14 R7C15 R7C16 R7C17 R7C18 R7C19 R7C20
PR8
PL8
R8C1
R8C2
R8C3
R8C4
R8C5
R8C6
R8C7
R8C8
R8C9
R8C10
R8C11 R8C12 R8C13 R8C14 R8C15 R8C16 R8C17 R8C18 R8C19 R8C20
PR9
PL9
R8C1
R9C2
R9C3
R9C4
R9C5
R9C6
R9C7
R9C8
R9C9
R9C10
R9C11 R9C12 R9C13 R9C14 R9C15 R9C16 R9C17 R9C18 R9C19 R9C20
PR10
PL10
R10C1 R10C2 R10C3 R10C4 R10C5 R10C6 R10C7 R10C8 R10C9 R10C10
R10C11 R10C12 R10C13 R10C14 R10C15 R10C16 R10C17 R10C18 R10C19 R10C20
RMID
LMID
hIQ
PL11
PR11
R11C1 R11C2 R11C3 R11C4 R11C5 R11C6 R11C7 R11C8 R11C9 R11C10
R11C11 R11C12 R11C13 R11C14 R11C15 R11C16 R11C17 R11C18 R11C19 R11C20
PL12
PR12
R12C1 R12C2 R12C3 R12C4 R12C5 R12C6 R12C7 R12C8 R12C9 R12C10
R12C11 R12C12 R12C13 R12C14 R12C15 R12C16 R12C17 R12C18 R12C19 R12C20
PR13
PL13
R13C1 R13C2 R13C3 R13C4 R13C5 R13C6 R13C7 R13C8 R13C9 R13C10
R13C11 R13C12 R13C13 R13C14 R13C15 R13C16 R13C17 R13C18 R13C19 R13C20
PR14
PL14
R14C1 R14C2 R14C3 R14C4 R14C5 R14C6 R14C7 R14C8 R14C9 R14C10
R14C11 R14C12 R14C13 R14C14 R14C15 R14C16 R14C17 R14C18 R14C19 R14C20
PL15
PR15
R15C1 R15C2 R15C3 R15C4 R15C5 R15C6 R15C7 R15C8 R15C9 R15C10
R15C11 R15C12 R15C13 R15C14 R15C15 R15C16 R15C17 R15C18 R15C19 R15C20
PL16
PR16
R16C1 R16C2 R16C3 R16C4 R16C5 R16C6 R16C7 R16C8 R16C9 R16C10
R16C11 R16C12 R16C13 R16C14 R16C15 R16C16 R16C17 R16C18 R16C19 R16C20
PR17
PL17
R17C1 R17C2 R17C3 R17C4 R17C5 R17C6 R17C7 R17C8 R17C9 R17C10
R17C11 R17C12 R17C13 R17C14 R17C15 R17C16 R17C17 R17C18 R17C19 R17C20
PL18
PR18
R18C1 R18C2 R18C3 R18C4 R18C5 R18C6 R18C7 R18C8 R18C9 R18C10
R18C11 R18C12 R18C13 R18C14 R18C15 R18C16 R18C17 R18C18 R18C19 R18C20
PL19
PR19
R19C1 R19C2 R19C3 R19C4 R19C5 R19C6 R19C7 R19C8 R19C9 R19C10
R19C11 R19C12 R19C13 R19C14 R19C15 R19C16 R19C17 R19C18 R19C19 R19C20
PL20
PR20
R20C1 R20C2 R20C3 R20C4 R20C5 R20C6 R20C7 R20C8 R20C9 R20C10
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
BMID
R20C11 R20C12 R20C13 R20C14 R20C15 R20C16 R20C17 R20C18 R20C19 R20C20
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
5-4489(C)
Figure 1. OR2C15A/OR2T15A Array
ORCA
Foundry Development System Overview
The
ORCA
Foundry Development System interfaces to front-end design entry tools and provides the tools to pro-
duce a configured FPGA. In the design flow, the user defines the functionality of the FPGA at two points in the
design flow: at design entry and at the bit stream generation stage.
Following design entry, the development system’s map, place, and route tools translate the netlist into a routed
FPGA. Its bit stream generator is then used to generate the configuration data which is loaded into the FPGA’s
internal configuration RAM. When using the bit stream generator, the user selects options that affect the functional-
ity of the FPGA. Combined with the front-end tools,
ORCA
Foundry produces configuration data that implements
the various logic and routing options discussed in this data sheet.
4
Lucent Technologies Inc.
Data Sheet
August 1996
ORCA
OR2CxxA and OR2TxxA Series FPGAs
Architecture
The
ORCA
Series FPGA is comprised of two basic
elements: PLCs and PICs. Figure 1 shows an array of
programmable logic cells (PLCs) surrounded by pro-
grammable input/output cells (PICs). The OR2C/2T15A
has PLCs arranged in an array of 20 rows and 20 col-
umns. PICs are located on all four sides of the FPGA
between the PLCs and the IC edge.
The location of a PLC is indicated by its row and col-
umn so that a PLC in the second row and third column
is R2C3. PICs are indicated similarly, with PT (top) and
PB (bottom) designating rows and PL (left) and PR
(right) designating columns, followed by a number. The
routing resources and configuration RAM are not
shown, but the interquad routing blocks (hIQ, vIQ)
present in the OR2CxxA/OR2TxxA series are shown.
Each PIC contains the necessary I/O buffers to inter-
face to bond pads. The PICs also contain the routing
resources needed to connect signals from the bond
pads to/from PLCs. The PICs do not contain any user-
accessible logic elements, such as flip-flops.
Combinatorial logic is done in look-up tables (LUTs)
located in the PFU. The PFU can be used in different
modes to meet different logic requirements. The LUT’s
configurable medium-/large-grain architecture can be
used to implement from one to four combinatorial logic
functions. The flexibility of the LUT to handle wide input
functions as well as multiple smaller input functions
maximizes the gate count/PFU.
The LUTs can be programmed to operate in one of
three modes: combinatorial, ripple, or memory. In com-
binatorial mode, the LUTs can realize any four-, five-,
or six-input logic functions. In ripple mode, the high-
speed carry logic is used for arithmetic functions, the
new multiplier function, or the enhanced data path
functions. In memory mode, the LUTs can be used as a
16 x 4 read/write or read-only memory (asynchronous
mode or the new synchronous mode) or a new 16 x 2
dual-port memory.
Programmable Logic Cells
The programmable logic cell (PLC) consists of a pro-
grammable function unit (PFU) and routing resources.
All PLCs in the array are identical. The PFU, which con-
tains four LUTs and four latches/FFs for logic imple-
mentation, is discussed in the next section.
Programmable Function Unit
The PFUs are used for logic. Each PFU has 19 exter-
nal inputs and six outputs and can operate in several
modes. The functionality of the inputs and outputs
depends on the operating mode.
The PFU uses three input data buses (a[4:0], b[4:0],
wd[3:0]), four control inputs (c0, ck, ce, lsr), and a carry
input (cin); the last is used for fast arithmetic functions.
There is a 5-bit output bus (o[4:0]) and a carry-out
(cout).
Figure 2 and Figure 3 show high-level and detailed
views of the ports in the PFU, respectively. The ports
are referenced with a two- to four-character suffix to a
PFU’s location. As mentioned, there are two 5-bit input
data buses (a[4:0] and b[4:0]) to the LUT, one 4-bit
input data bus (wd[3:0]) to the latches/FFs, and an out-
put data bus (o[4:0]).
PROGRAMMABLE LOGIC CELL (PLC)
wd3
wd2
wd1
wd0
a4
a3
a2
a1
a0
b4
b3
b2
b1
b0
cin
c0 ck
ce
lsr
cout
o4
o3
o2
o1
o0
PROGRAMMABLE
FUNCTION UNIT
(PFU)
(ROUTING RESOURCES, CONFIGURATION RAM)
5-2750(F)
Figure 2. PFU Ports
Lucent Technologies Inc.
5
京公网安备 11010802033920号
EEWORLD
