IBIS5-B-1300
CYII5FM1300AB
1.3 MP CMOS Image Sensor
Description
The IBIS5-B-1300 is a solid state CMOS image sensor that
integrates the functionality of complete analog image acqui-
sition, digitizer and digital signal processing system on a single
chip. This 1.3-mega pixel (1280 x 1024) CMOS active pixel
sensor dedicated to industrial vision applications features both
rolling and snapshot (or global) shutter. Full frame readout
time is 36 ms (max. 27.5 fps), and readout speed can be
boosted by windowed region of interest (ROI) readout. High
dynamic range scenes can be captured using the double and
multiples slope functionality. The sensor is available in a
Monochrome version or Bayer (RGB) patterned color filter
array.
User programmable row and column start/stop positions allow
windowing down to a 2x1 pixel window for digital zoom. Sub
sampling or viewfinder mode reduces resolution while
maintaining the constant field of view and an increased frame
rate. The analog video output of the pixel array is processed
by an on-chip analog signal pipeline. Double Sampling (DS)
eliminates the fixed pattern noise. The programmable gain and
offset amplifier maps the signal swing to the ADC input range.
A 10-bit ADC converts the analog data to a 10-bit digital word
stream. The sensor uses an 2-wire, I2C™-compatible,
interface, a 3-wire Serial-Parallel (SPI) interface, or a 16-bit
parallel interface. It operates with a 3.3V power supply and
requires only one master clock for operation up to 40 MHz. It
is housed in an 84-pin ceramic LCC package.
Table 1. Key Performance Parameters
Parameter
Active Pixels
Pixel Size
Optical format
Shutter Type
Maximum Data Rate /
Master Clock
Frame rate
ADC resolution
Sensitivity (@ 650 nm)
S/N Ratio
Full Well Charge
Temporal Noise
Dark current
High Dynamic Range
Supply Voltage
Typical Value
1280 (H) x 1024 (V)
6.7
µm
x 6.7
µm
2/3 inch
Snapshot (Global) Shutter
Rolling Shutter
40 MPS / 40 MHz
27 fps (1280 x 1024)
106 fps (640 x 480)
10-bit, on-chip
715 V.m2/W.s
8.40 V/lux.s
64 dB
62.500 e–
40 e–
7.22 mV/s
Multiple Slope
Analog: 3.0V–4.5V
Digital: 3.3V
I/O: 3.3V
175 mW
–30°C to +65°C
Mono
RGB Bayer Pattern
84-pins LCC
Applications
•
•
•
•
·Machine vision
·Inspection
·Robotics
·Traffic monitoring
Power consumption
Operating temperature
Color Filter Array
Packaging
Cypress Semiconductor Corporation
Document #: 38-05710 Rev. *A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 11, 2007
IBIS5-B-1300
CYII5FM1300AB
Architecture and Operation
In this part the most important blocks of the sensor are described in more detail.
Floor Plan
Figure 1. Block Diagram of the IBIS5-B-1300 Image Sensor
Sensor
Imager core
Reset
C
Y-right
addressing
Sample
Select
Pixel
Y-left
addressing
Column output
Pixel core
Sequencer
Column amplifiers
Analog multiplexer
Output
amplifier
System clock
40 MHz
External
connection
X-addressing
ADC
Figure 1
shows the architecture of the IBIS5-B-1300 image
sensor. It consists basically of a pixel array, one X- and two
Y-addressing registers for the readout in X- and Y-direction,
column amplifiers that correct for the fixed pattern noise, an
analog multiplexer, and an analog output amplifier.
The left Y-addressing register is used for readout operation.
The right Y-addressing register is used for reset of pixel rows.
In multiple slope synchronous shutter mode, the right
Y-addressing register resets the whole pixel core with a
lowered reset voltage. In rolling curtain shutter mode, the right
Y-addressing register is used for the reset pointer in single and
double slope operation to reset 1 pixel row.
Most of the signals for the image core are generated by the
on-chip sequencer. Some basic signals (like start/stop
integration, line and frame sync signals, etc.) have to be
generated externally.
A 10-bit ADC is implemented on chip but electrically isolated
from the image core. The analog pixel output has to be routed
to the analog ADC input on the outside.
Pixel
The pixel architecture and the color filter array are described
below.
Architecture
The pixel architecture used in the IBIS5-B-1300 is a
4-transistor pixel as shown in
Figure 2.
The pixel has been
implemented using the high fill factor technique as patented by
Cypress (US patent No. 6,225,670 and others). The 4T-pixel
features a snapshot shutter but can also emulate the 3T-pixel
by continuously closing sampling switch M2. Using M4 as a
global sample transistor for all pixels enables the snapshot
shutter mode. Due to this pixel architecture, integration during
read out is not possible in synchronous shutter mode.
Figure 2. Architecture of the 4T-pixel
M1
reset
C
M2
sample
M3
mux
M4
column
output
Page 2 of 42
Document #: 38-05710 Rev. *A
IBIS5-B-1300
CYII5FM1300AB
Color Filter Array
The IBIS5-B-1300 can also be processed with a Bayer RGB
color pattern. Pixel (0,0) has a green filter and is situated on a
green-blue row. Green1 and green2 have a slightly different
spectral response due to cross talk from neighboring pixels.
Green1 pixels are located on a blue-green row, green2 pixels
are located on a green-red row.
Figure 4
below shows the
response of the color filter array as function of the wavelength.
Note that this response curve includes the optical cross talk of
the pixels.
Figure 3. Color Filter Arrangement on the Pixels
Red
Green2
baseline, see also
“Internal Clock Granularities (bits 4, 5, 6 and
7).” on page 13),
this requires a minimum pixel rate of nearly
40 MHz. The final bandwidth of the column amplifiers, output
stage, and others is determined by external bias resistors.
With a nominal pixel rate of 40 MHz, a full frame rate of a little
more than 27 frames per second is obtained.
The frame period of the IBIS5-B-1300 sensor depends on the
shutter type.
Rolling Shutter
=> Frame period = (Nr. Lines * (RBT + pixel period * Nr.
Pixels))
with:
Nr. Lines: Number of Lines read out each frame (Y).
Nr. Pixels: Number of pixels read out each line (X).
RBT: Row Blanking Time = 3.5 ms (typical).
Pixel period: 1/40 MHz = 25 ns.
Example
Read out time of the full resolution at nominal speed
(40-MHz pixel rate):
Green1
Blue
Red
Green2
Red
Green2
Green1
Blue
Green1
Blue
=> Frame period = (1024 * (3.5 ms + 25 ns * 1280)) = 36.4 ms
=> 27.5 fps.
Snapshot shutter
=> Frame period = Tint + Tread out
= Tint + (Nr. Lines * (RBT + pixel period * Nr. Pixels))
with:
Tint: Integration (exposure) time.
Nr. Lines: Number of Lines read out each frame (Y).
Nr. Pixels: Number of pixels read out each line (X).
Pixel 0,0
Frame Rate
The pixel rate for this sensor is high enough to support a frame
rate of >100 Hz for a window size of 640 x 480 pixels (VGA
format). Taking into account a row blanking time of 3.5 ms (as
Figure 4. Color Filter Response
Wavelength (nm)
Document #: 38-05710 Rev. *A
Page 3 of 42
IBIS5-B-1300
CYII5FM1300AB
RBT: Row Blanking Time = 3.5 ms (typical).
Pixel period: 1/40 MHz = 25 ns.
Example
Read out time of the full resolution at nominal speed
(40 MHz pixel rate) with an integration time of 1 ms:
Image Core Operation
Image Core Operation and Signalling
Figure 5
is a functional representation of the image core
without sub-sampling and column/row swapping circuits. Most
of the involved signals are not available from the outside
because they are generated by the X-sequencer and
SS-sequencer blocks.
The integration of the pixels is controlled by internal signals
such as reset, sample, hold are generated by the on-chip
SS-sequencer that is controlled with the external signals
SS_START and SS_STOP. Reading out the pixel array starts
by applying a Y_START together with a Y_CLOCK signal;
internally this is followed by a calibration sequence to calibrate
the output amplifiers (during the row blanking time); signals
necessary to do this calibration are generated by the on-chip
X-sequencer. This calibration sequence takes typically 3.5
µ
s
and is necessary to remove Fixed Pattern Noise of the pixels
and of the column amplifiers themselves by means of a Double
Sampling technique. After the row blanking time the pixels are
fed to the output amplifier. The pixel rate is equal to the
SYS_CLOCK frequency.
Image Core Supply Considerations
The image sensor has several supply voltages:
VDDH is the voltage that controls the sample switches and
must always be the highest voltage that is applied to the chip.
The VDDR_LEFT voltage is the highest (nominal) reset
voltage of the pixel core.
=> Frame period = 1 ms + (1024 * (3.5 ms + 25 ns * 1280)) =
37.4 ms => 26.8 fps.
Region-Of-Interest (ROI) Read Out
Windowing can easily be achieved by uploading the starting
point of the x- and y-shift registers in the sensor registers using
the various interfaces. This downloaded starting point initiates
the shift register in the x- and y-direction triggered by the
Y_START (initiates the Y-shift register) and the Y_CLK
(initiates the X-shift register) pulse. The minimum step size for
the x-address is 2 (only even start addresses can be chosen)
and 1 for the Y-address (every line can be addressed). The
frame rate increases almost linearly when fewer pixels are
read out.
Table 2
gives an overview of the achievable frame
rates (in rolling shutter mode) with various ROI dimensions.
Table 2. Frame Rate vs. Resolution
Image
Resolution
(X*Y)
Frame
Frame Rate Readout Time
[frames/s]
[ms]
Comment
1280 x 1024
640 x 480
100 x 100
27
100
1657
36
10
0.6
Full resolution.
ROI read out.
ROI read out.
Figure 5. Image Core
Vddreset
VDDR_LEFT
VDDH
SAMPLE
RESET
HOLD
VDDR_RIGHT
Pixel row
Y-left addressing
Y_START
Y_CLOCK
Pixel
A
Pixel column
Pixel
B
Y-right addressing
Y_START
Y_CLOCK
VDDC
Column amplifiers
Read-pointer
Output amplifier
BUS_A
BUS_B
X addressing
PXL_OUT
SYS_CLOCK
Document #: 38-05710 Rev. *A
Page 4 of 42
IBIS5-B-1300
CYII5FM1300AB
The VDDR_RIGHT voltage is generated from the
VDDR_LEFT voltage using a circuit that can be programmed
with the KNEEPOINT_LSB/MSB bits in the sequencer register
(see also
“Pixel Reset Knee-point for Multiple Slope Operation
(bits 8, 9, and 10).” on page 14).
By setting the
VDDR_RIGHT_EXT bit in the SEQUENCER register, the
VDDR_RIGHT pin can be disconnected from the circuit and
an external voltage can be applied to supply the multiple slope
reset voltage. When no external voltage is applied (recom-
mended) the VDDR_RIGHT pin should be connected to a
capacitor (recommended value = 1µF). VDDC is the supply of
the pixel core. VDDA is the analog supply of the image core
and periphery. VDDD is the digital supply of the image core
and periphery.
Note that the IBIS5-B-1300 image sensor has no power
rejection circuitry on-chip. As a consequence all variations on
the analog supply voltages can contribute to random variations
(noise) on the analog pixel signal, which is seen as random
noise in the image. During the camera design precautions
have to be taken to supply the sensor with very stable supply
voltages to avoid this additional noise. Especially the analog
supplies of the pixel array (VDDR_LEFT, VDDH and VDDC)
are vulnerable for this.
Snapshot Shutter Supply Considerations
When using the IBIS5-B-1300 sensor in snapshot shutter
mode only the recommended supply voltage settings are listed
below in
Table 3.
Table 3. Snapshot Shutter Recommended Supply
Settings
Parameter
VDDH
VDDR_LEFT
VDDC
VDDA
Description
Voltage on HOLD switches.
Highest reset voltage.
Pixel core voltage.
Analog supply voltage of the
image core.
Digital supply voltage of the
image core.
Analog ground.
Digital ground.
Anti-blooming ground.
Typ.
+4.5
+4.5
+3.3
+3.3
Unit
V
V
V
V
Dual Shutter Supply Considerations
With the supply settings listed in
Table 3
some fixed column
non-uniformities (FPN) can be seen when operating in rolling
shutter mode. If a dual shutter mode (both rolling and snapshot
shutter) is required during operation one needs to apply the
supply settings listed in
Table 4
below to achieve the best
possible image quality.
Table 4. Dual Shutter Recommended Supply Settings
Parameter
Description
Typ. Unit
VDDH
VDDC
VDDA
VDDD
GNDA
GNDD
GND_AB
Voltage on HOLD switches.
Pixel core voltage.
Analog supply voltage of the
image core.
Digital supply voltage of the
image core.
Analog ground.
Digital ground.
Anti-blooming ground.
+4.5
+4.5
+3.0
+3.3
+3.3
0
0
0
V
V
V
V
V
V
V
V
VDDR_LEFT Highest reset voltage.
Image Core Biasing Signals
Table 5
summarizes the biasing signals required to drive the
IBIS5-A-1300. For optimizations reasons with respect to
speed and power dissipation of all internal block several
biasing resistors are needed.
Each biasing signal determines the operation of a corre-
sponding module in the sense that it controls the speed and
power dissipation. The tolerance on the DC-level of the bias
levels can vary ±150 mV due to process variations.
VDDD
GNDA
GNDD
GND_AB
+3.3
0
0
0
V
V
V
V
Table 5. Overview of Bias Signals
Signal
Comment
Related module
DC-level
DEC_CMD
Connect to VDDA with R = 50 k
Ω
and decouple to GNDA with C = 100 nF. Decoder stage.
High level of DAC.
Low level of DAC.
1.0V
3.3V
0.0V
1.2V
1.0V
1.1V
1.0V
2.7V
1.8V
Page 5 of 42
DAC_VHIGH Connect to VDDA with R = 0
Ω
.
DAC_VLOW Connect to GNDA with R = 0
Ω
.
AMP_CMD
COL_CMD
PC_CMD
ADC_CMD
Connect to VDDA with R = 50 k
Ω
and decouple to GNDA with C = 100 nF. Output amplifier stage.
Connect to VDDA with R = 50 k
Ω
and decouple to GNDA with C = 100 nF. Columns amplifiers stage.
Connect to VDDA with R = 25 k
Ω
and decouple to GNDA with C = 100 nF. Pre-charge of column
busses.
Connect to VDDA with R = 50 k
Ω
and decouple to GNDA with C = 100 nF. Analog stage of ADC.
ADC_VHIGH Connect to VDDA with R = 360
Ω
and decouple to GNDA with C = 100 nF. High level of ADC.
ADC_VLOW Connect to GNDA with R = 1200
Ω
and decouple to GNDA with C = 100 nF. Low level of ADC.
Document #: 38-05710 Rev. *A
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