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LTC2285IUP-3CGPBF

Description
2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
Categorysemiconductor    logic   
File Size579KB,24 Pages
ManufacturerLinear ( ADI )
Websitehttp://www.analog.com/cn/index.html
Download Datasheet Parametric Compare View All

LTC2285IUP-3CGPBF Overview

2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64

LTC2285IUP-3CGPBF Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals64
Maximum operating temperature85 Cel
Minimum operating temperature-40 Cel
Rated supply voltage3 V
Maximum limit analog input voltage1 V
Minimum limit analog input voltage-0.5000 V
Processing package description9 X 9 MM, PLASTIC, MO-220WNJR-5, QFN-64
stateACTIVE
CraftsmanshipCMOS
packaging shapeSQUARE
Package SizeCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
surface mountYes
Terminal formNO LEAD
Terminal spacing0.5000 mm
terminal coatingTIN LEAD
Terminal locationQUAD
Packaging MaterialsPLASTIC/EPOXY
Temperature levelINDUSTRIAL
Sampling Rate125 MHz
Output formatPARALLEL, WORD
Type of converterPROPRIETARY METHOD
Number of digits14
Output bit encodingOFFSET BINARY, 2S COMPLEMENT BINARY
Number of analog channels2
Sample and hold and track and holdSAMPLE
FEATURES
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LTC2285IUP#3CGPBF
Dual 14-Bit, 135Msps
Low Power 3.3V ADC
DESCRIPTION
The LTC
®
2285IUP#3CGPBF is a 14-bit 135Msps, low
power dual 3.3V A/D converter designed for digitiz-
ing high frequency, wide dynamic range signals. The
LTC2285IUP#3CGPBF is perfect for demanding imaging
and communications applications with AC performance
that includes 72.2dB SNR and 82dB SFDR for signals at
the Nyquist frequency.
Typical DC specs include
±1.5LSB
INL,
±0.6LSB
DNL. The
transition noise is a low 1.3LSB
RMS
.
A single 3.3V supply allows low power operation. A
separate output supply allows the outputs to drive 0.5V
to 3.6V logic.
A single-ended CLK input controls converter operation.
An optional clock duty cycle stabilizer allows high perfor-
mance at full speed for a wide range of clock duty cycles.
A data ready output clock (CLKOUT) can be used to latch
the output data.
L,
LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
n
Integrated Dual 14-Bit ADCs
Sample Rate: 135Msps
Single 3.3V Supply (2.85V to 3.4V)
Low Power: 954mW
72.4dB SNR, 88dB SFDR
110dB Channel Isolation at 100MHz
Flexible Input: 1V
P-P
to 2V
P-P
Range
640MHz Full Power Bandwidth S/H
Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Data Ready Output Clock
Pin Compatible Family
125Msps: LTC2283 (12-Bit), LTC2285 (14-Bit)
105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit)
80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)
65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)
40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)
64-Pin (9mm
×
9mm) QFN Package
APPLICATIONS
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Wireless and Wired Broadband Communication
Imaging Systems
Spectral Analysis
Portable Instrumentation
TYPICAL APPLICATION
+
ANALOG
INPUT A
INPUT
S/H
OV
DD
14-BIT
PIPELINED
ADC CORE
OUTPUT
DRIVERS
D13A
D0A
OGND
SNR (dBFS)
SNR vs Input Frequency,
–1dB, 2V Range
75
74
73
72
71
70
69
68
67
66
CLK A
CLOCK/DUTY CYCLE
CONTROL
CLOCK/DUTY CYCLE
CONTROL
OF
MUX
CLK B
CLKOUT
OV
DD
65
0
50
+
ANALOG
INPUT B
INPUT
S/H
14-BIT
PIPELINED
ADC CORE
OUTPUT
DRIVERS
D13B
D0B
OGND
2285 TA01
100 150 200 250 300 350
2285 TA01b
INPUT FREQUENCY (MHz)
2285iup#3cgpbf
1

LTC2285IUP-3CGPBF Related Products

LTC2285IUP-3CGPBF LTC2285IUP LTC2285UP
Description 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
Number of functions 1 1 1
Number of terminals 64 64 64
Maximum operating temperature 85 Cel 85 °C 85 Cel
Minimum operating temperature -40 Cel -40 °C -40 Cel
surface mount Yes YES Yes
Terminal form NO LEAD NO LEAD NO LEAD
Terminal location QUAD QUAD QUAD
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL
Output format PARALLEL, WORD PARALLEL, WORD PARALLEL, WORD
Number of digits 14 14 14
Rated supply voltage 3 V - 3 V
Maximum limit analog input voltage 1 V - 1 V
Minimum limit analog input voltage -0.5000 V - -0.5000 V
Processing package description 9 X 9 MM, PLASTIC, MO-220WNJR-5, QFN-64 - 9 X 9 MM, PLASTIC, MO-220WNJR-5, QFN-64
state ACTIVE - ACTIVE
Craftsmanship CMOS - CMOS
packaging shape SQUARE - SQUARE
Package Size CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE - CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Terminal spacing 0.5000 mm - 0.5000 mm
terminal coating TIN LEAD - TIN LEAD
Packaging Materials PLASTIC/EPOXY - PLASTIC/EPOXY
Sampling Rate 125 MHz - 125 MHz
Type of converter PROPRIETARY METHOD - PROPRIETARY METHOD
Output bit encoding OFFSET BINARY, 2S COMPLEMENT BINARY - OFFSET BINARY, 2S COMPLEMENT BINARY
Number of analog channels 2 - 2
Sample and hold and track and hold SAMPLE - SAMPLE

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