530MA830M000BGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 530MA830M000BGR

530MA830M000BGR: DescriptionLVPECL Output Clock Oscillator, 830MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size268KB，15 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530MA830M000BGR Overview

LVPECL Output Clock Oscillator, 830MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530MA830M000BGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	50%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	830 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.0 7/06

Si530/531

Recommended Resources

Pulse boost circuitb

Wiring b when leakage protector in TT system supplies single-phase load

HT-1370 circuit

300uA floating current source circuit diagram

Belt conveyor stall protection circuit

Computer motherboard circuit diagram 820 2_01

Portability of djyos (Part 2): [b][color=#000000][font=Arial][font=Arial][size=5]1.[/size][/font] [/font][font=新宋体][size=5]Data width and alignment[/size][/font][/color][/b] [align=left][color=#000000] In embedded development, for ...; djyos Real-time operating system RTOS

Let’s talk about the blood and tears of buying electronic components(...): I believe everyone has bought electronic components themselves. Faced with a variety of sales channels, how do you ensure that you can buy genuine components? Some components are too mature and there ...; 辛昕 Buy&Sell

Embedded Multimedia Platform Based on PNX1500: With the development of system-on-chip design technology, embedded technology plays an increasingly important role in the IT industry. Multimedia applications are an important aspect of embedded syste...; 呱呱 Embedded System

Delta VFD-P 11KW "CFF" fault, still not fixed!: I would like to ask about the "CFF" fault of Delta VFD-P series 11KW. A Delta VFD-P series 11KW inverter drives a load with large inertia (with an external BRAKE unit). It was normal before, but now i...; eeleader Industrial Control Electronics

【allegro】How to divide a whole picture into two and turn it into two signals!: [Repost] Author: Xinying [p=26, null, left][color=rgb(0, 0, 0)] Normally, we will lay the ground copper and power copper on the whole board, but if the principle suddenly changes, we need to change th...; ohahaha PCB Design

Questions about simulation in Quartus: It's like this. I wrote a small Verilog program, compiled it successfully, and then after creating the bdf file, I compiled it again, but an error occurred. The error is: Error: Can't compile duplicat...; zany.peng Embedded System

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components