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HY62V16100LLR2-I-85

Description
Standard SRAM, 128KX8, 85ns, CMOS, PDSO44, 0.400 INCH, REVERSE, TSOP2-44
Categorystorage    storage   
File Size152KB,10 Pages
ManufacturerSK Hynix
Websitehttp://www.hynix.com/eng/
Download Datasheet Parametric View All

HY62V16100LLR2-I-85 Overview

Standard SRAM, 128KX8, 85ns, CMOS, PDSO44, 0.400 INCH, REVERSE, TSOP2-44

HY62V16100LLR2-I-85 Parametric

Parameter NameAttribute value
Parts packaging codeTSOP2
package instructionTSOP2-R,
Contacts44
Reach Compliance Codeunknown
ECCN codeEAR99
Maximum access time85 ns
JESD-30 codeR-PDSO-G44
JESD-609 codee6
length18.41 mm
memory density1048576 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals44
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize128KX8
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2-R
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN BISMUTH
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationDUAL
width10.16 mm
Base Number Matches1
HY62V16100-(I)/HY62U16100-(I) Series
64Kx16bit CMOS SRAM
DESCRIPTION
The HY62V16100-(I)/HY62U16100-(I) is a high-
speed, low power and 1M bits CMOS SRAM
organized as 65,536 words by 16 bits. The
HY62V16100-(I)/ HY62U16100-(I) uses sixteen
common input and output lines and has an output
enable pin which operates faster than address
access time at a read cycle. The device is
fabricated using HYUNDAI's advanced CMOS
process and designed with high-speed low power
circuit technology. It is particulary well suited for
being used in high-density and low power system
applications.
FEATURES
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Data Byte Control
- LB : I/O1 ~ I/O8, UB : I/O9 ~ I/O16
Battery backup(L/LL-part)
- 2.0V(min) data retention
Standard pin configuration
- 44pin 400mil TSOP-II
(Standard and Reversed)
Product
Supply
Speed
Operation
Standby Current(uA)
No.
Voltage(V)
(ns)
Current(mA)
L
LL
HY62V16100
3.3
85/100/120
5
50
10
HY62V16100-I
3.3
85/100/120
5
50
15
HY62U16100
3.0
100/120/150
5
50
10
HY62U16100-I
3.0
100/120/150
5
50
10
Note 1. E.T. : Extended Temperature, Normal : Normal Temperature
2. Current value is max.
Temperature.
(°C)
0~70(Normal)
-40~85(E.T.)
0~70(Normal)
-40~85(E.T.)
PIN CONNECTION
BLOCK DIAGRAM
SENSE AMP
A1~A7
ADD INPUT
BUFFER
ROW
DECODER
I/O1
A4
A3
A2
A1
A0
/CS
I/O1
I/O2
I/O3
I/O4
Vcc
GND
I/O5
I/O6
I/O7
I/O8
/WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
/OE
/UB
/LB
I/O16
I/O15
I/O14
I/O13
GND
Vcc
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
NC
NC
A12
A13
A14
A15
/WE
I/O8
I/O7
I/O6
I/O5
GND
Vcc
I/O4
I/O3
I/O2
I/O1
/CS
A0
A1
A2
A3
A4
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
NC
A11
A10
A9
A8
NC
I/O9
I/O10
I/O11
I/O12
Vcc
GND
I/O13
I/O14
I/O15
I/O16
/LB
/UB
/OE
A7
A6
A5
A14
A15
A8
A9
A10
A11
A12
A13
A0
/CS
/OE
/LB
/UB
/WE
PRE-DECODER
COLUMN
DECODER
ADD INPUT
BUFFER
MEMORY ARRAY
512x128x16
WRITE DRIVER
OUTPUT
BUFFER
I/O8
I/O9
ADD INPUT
BUFFER
BLOCK
DECODER
I/O16
TSOP-II(Standard)
TSOP-II(Reversed)
PIN DESCRIPTION
Pin Name
/CS
/WE
/OE
/LB
/UB
Pin Funtion
Chip Select
Write Enable
Output Enable
Low Byte Control(I/O1~I/O8)
Upper Byte Control(I/O9~I/O16)
Pin Name
I/O1~I/O16
A0~A15
Vcc
Vss
NC
Pin Funtion
Data Input/Output
Address Input
Power(3.3V/3.0V)
Ground
No Connection
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.07 /Jan.99
Hyundai Semiconductor
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