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CY7C006A-15ACT

Description
Dual-Port SRAM, 16KX8, 15ns, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-64
Categorystorage    storage   
File Size335KB,20 Pages
ManufacturerCypress Semiconductor
Download Datasheet Parametric View All

CY7C006A-15ACT Overview

Dual-Port SRAM, 16KX8, 15ns, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-64

CY7C006A-15ACT Parametric

Parameter NameAttribute value
Parts packaging codeQFP
package instructionLQFP,
Contacts64
Reach Compliance Codeunknown
ECCN codeEAR99
Maximum access time15 ns
JESD-30 codeS-PQFP-G64
length14 mm
memory density131072 bit
Memory IC TypeDUAL-PORT SRAM
memory width8
Number of functions1
Number of terminals64
word count16384 words
character code16000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize16KX8
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationQUAD
width14 mm
Base Number Matches1
CY7C006A
CY7C007A
CY7C017A32K/16K x 8, 32K x 9
Dual-Port Static RAM
CY7C006A/CY7C007A
CY7C016A/CY7C017A
32K/16K x 8, 32K x 9
Dual-Port Static RAM
Features
• True dual-ported memory cells which allow
simultaneous access of the same memory location
• 16K x 8 organization (CY7C006A)
• 32K x 8 organization (CY7C007A)
• 16K x 9 organization (CY7C016A)
• 32K x 9 organization (CY7C017A)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 12
[1]
/15/20 ns
• Low operating power
— Active: I
CC
= 180 mA (typical)
— Standby: I
SB3
= 0.05 mA (typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 16/18 bits or more using
Master/Slave chip select when using more than one
device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flags for port-to-port communication
• Pin select for Master or Slave
• Commercial temperature range
• Available in 68-pin PLCC (CY7C006A, CY7C007A and
CY7C017A), 64-pin TQFP (CY7C006A), and in 80-pin
TQFP (CY7C007A and CY7C016A)
• Pb-Free packages available
Logic Block Diagram
R/W
L
CE
L
OE
L
R/W
R
CE
R
OE
R
[2]
8/9
8/9
[2]
I/O
0L
–I/O
7/8L
I/O
Control
I/O
Control
I/O
0R
–I/O
7/8R
14/15
[4]
A
0L
–A
13/14L
Address
Decode
14/15
True Dual-Ported
RAM Array
Address
Decode
14/15
14/15
A
0R
–A
13/14R
[4]
[4]
A
0L
–A
13/14L
CE
L
OE
L
R/W
L
SEM
L
Interrupt
Semaphore
Arbitration
BUSY
L
INT
L
[3]
A
0R
–A
13/14R
CE
R
OE
R
R/W
R
SEM
R
[3]
[4]
BUSY
R
INT
R
M/S
Notes:
1. See page 7 for Load Conditions.
2. I/O
0
–I/O
7
for x8 devices; I/O
0
–I/O
8
for x9 devices.
3. BUSY is an output in master mode and an input in slave mode.
4. A
0
–A
13
for 16K; A
0
–A
14
for 32K devices.
Cypress Semiconductor Corporation
Document #: 38-06045 Rev. *D
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised August 11, 2005
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