LAN9420I-NU datasheet, PDF - EEWORLD Datasheet

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LAN9420I-NU: DescriptionLAN Controller, 3 Channel(s), 12.5MBps, CMOS, PQFP128, ROHS COMPLIANT, VTQFP-128; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，171 Pages; ManufacturerSMSC; Websitehttp://www.smsc.com/; Environmental Compliance

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LAN9420I-NU Overview

LAN Controller, 3 Channel(s), 12.5MBps, CMOS, PQFP128, ROHS COMPLIANT, VTQFP-128

LAN9420I-NU Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	QFP
package instruction	TFQFP, TQFP128,.63SQ,16
Contacts	128
Reach Compliance Code	unknown
Address bus width
boundary scan	NO
Bus compatibility	PCI
maximum clock frequency	25 MHz
letter of agreement	SYNC, SDLC
Data encoding/decoding methods	NRZI; BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	12.5 MBps
External data bus width
JESD-30 code	S-PQFP-G128
length	14 mm
low power mode	YES
Number of serial I/Os	3
Number of terminals	128
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TFQFP
Encapsulate equivalent code	TQFP128,.63SQ,16
Package shape	SQUARE
Package form	FLATPACK, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum slew rate	145 mA
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.4 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches	1

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LAN9420/LAN9420i

Single-Chip Ethernet Controller

with HP Auto-MDIX Support and

PCI Interface

PRODUCT FEATURES

Highlights

Optimized for embedded applications with 32-bit

RISC CPUs

Integrated descriptor based scatter-gather DMA and

IRQ deassertion timer effectively increase network

throughput and reduce CPU loading

Integrated Ethernet MAC with full-duplex support

Integrated 10/100 Ethernet PHY with HP Auto-MDIX

support

32-bit, 33MHz, PCI 3.0 compliant interface

Reduced power operating modes with PCI Power

Management Specification 1.1 compliance

Supports multiple audio & video streams over

Ethernet

—

Datasheet

– Promiscuous mode

– Inverse filtering

– Pass all incoming with status report

Wakeup packet support

Integrated 10/100 Ethernet PHY

– Auto-negotiation

– Automatic polarity detection and correction

– Supports HP Auto-MDIX

– Supports energy-detect power down

Support for 3 status LEDs

Receive and transmit TCP checksum offload

—

PCI Interface

— PCI Local Bus Specification Revision 3.0 compliant

— 32-bit/33-MHz PCI bus

— Descriptor based scatter-gather DMA enables zero-

copy drivers

Comprehensive Power Management Features

— Supports PCI Bus Power Management Interface

Specification, Revision 1.1

— Supports optional wake from D3cold

(via configuration strap option when Vaux is available)

— Wake on LAN

— Wake on link status change (energy detect)

— Magic packet wakeup

Target Applications

Cable, satellite, and IP set-top boxes

Digital televisions

Digital video recorders

Home gateways

Digital media clients/servers

Industrial automation systems

Industrial/single board PC

Kiosk/POS enterprise equipment

General Purpose I/O

— 3 programmable GPIO pins

— 2 GPO pins

Support for Optional EEPROM

— Serial interface provided for EEPROM

— Used to store PCI and MAC address configuration

values

Key Benefits

Integrated High-Performance 10/100 Ethernet

Controller

—

Fully compliant with IEEE802.3/802.3u

Integrated Ethernet MAC and PHY

10BASE-T and 100BASE-TX support

Full- and half-duplex support

Full-duplex flow control

Preamble generation and removal

Automatic 32-bit CRC generation and checking

Automatic payload padding and pad removal

Loop-back modes

Flexible address filtering modes

– One 48-bit perfect address

– 64 hash-filtered multicast addresses

– Pass all multicast

Miscellaneous Features

— Big/Little/Mixed endian support for registers,

descriptors, and buffers

— IRQ deassertion timer

— General purpose timer

Single 3.3V Power Supply

— Integrated 1.8V regulator

Packaging

— Available in 128-pin VTQFP Lead-free RoHS Compliant

package

Environmental

— Available in commercial & industrial temperature ranges

SMSC LAN9420/LAN9420i

DATASHEET

Revision 1.6 (07-18-11)

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

Order Numbers:

LAN9420-NU For 128-PIN VTQFP, Lead-Free RoHS Compliant Package (0 to 70

LAN9420i-NU For 128-PIN VTQFP, Lead-Free RoHS Compliant Package (-40

to 85

This product meets the halogen maximum concentration values per IEC61249-2-21

For RoHS compliance and environmental information, please visit

www.smsc.com/rohs

80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000 or 1 (800) 443-SEMI

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for

construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC

reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications

before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent

rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated

version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors

known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not

designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property

damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of

this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered

trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,

FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE

OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL

DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;

TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD

TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

Revision 1.6 (07-18-11)

DATASHEET

SMSC LAN9420/LAN9420i

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

Table of Contents

Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.1

1.2

1.3

1.4

1.5

1.6

1.7

Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.7.1

Interrupt Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.7.2

PLL and Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.7.3

EEPROM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.7.4

GPIO/LED Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.7.5

General Purpose Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.7.6

Free Run Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Control and Status Registers (CSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.8

Chapter 2 Pin Description and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1

2.2

Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Chapter 3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.1

3.2

Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

PCI Bridge (PCIB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.2.1

PCI Bridge (PCIB) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.2.2

PCI Interface Environments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.2.3

PCI Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.2.3.1 PCI Master Transaction Errors....................................................................................... 25

3.2.4

PCI Target Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.2.4.1 PCI Configuration Space Registers ............................................................................... 26

3.2.4.2 Control and Status Registers (CSR) .............................................................................. 26

3.2.4.2.1 CSR Endianness....................................................................................................... 26

3.2.4.2.2 I/O Mapping of CSR.................................................................................................. 27

3.2.4.3 PCI Target Interface Transaction Errors ........................................................................ 27

3.2.4.4 PCI Discard Timer.......................................................................................................... 27

3.2.5

Interrupt Gating Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

System Control Block (SCB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.3.1

Interrupt Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.3.2

Wake Event Detection Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.3.3

General Purpose Timer (GPT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.3.4

Free-Run Counter (FRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.3.5

EEPROM Controller (EPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.3.5.1 EEPROM Format ...........................................................................................................31

3.3.5.2 MAC Address, Subsystem ID, and Subsystem Vendor ID Auto-Load ........................... 32

3.3.5.3 EEPROM Host Operations............................................................................................. 32

3.3.5.3.1 Supported EEPROM Operations .............................................................................. 34

3.3.5.3.2 Host Initiated MAC Address, SSID, SSVID Reload .................................................. 37

3.3.5.3.3 EEPROM Command and Data Registers .................................................................37

3.3.5.3.4 EEPROM Timing....................................................................................................... 37

3.3.6

System Control and Status Registers (SCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

DMA Controller (DMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.4.1

DMA Controller Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.3

3.4

SMSC LAN9420/LAN9420i

DATASHEET

Revision 1.6 (07-18-11)

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

3.5

3.6

3.4.2

Data Descriptors and Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.4.2.1 Receive Descriptors ....................................................................................................... 41

3.4.2.2 Transmit descriptors....................................................................................................... 45

3.4.3

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.4.4

Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.4.5

Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.4.6

Receive Descriptor Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.4.7

Suspend State Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.4.7.1 Transmit Engine ............................................................................................................. 51

3.4.7.2 Receive Engine .............................................................................................................. 51

3.4.8

Stopping Transmission and Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.4.9

TX Buffer Fragmentation Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.4.9.1 Calculating Worst-Case TX FIFO (MIL) Usage.............................................................. 52

3.4.10 DMAC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.4.11 DMAC Control and Status Registers (DCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10/100 Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.5.1

Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.5.1.1 Full-Duplex Flow Control................................................................................................54

3.5.2

Virtual Local Area Network (VLAN) Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.5.3

Address Filtering Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.5.3.1 Perfect Filtering .............................................................................................................. 56

3.5.3.2 Hash Only Filtering Mode............................................................................................... 56

3.5.3.3 Hash Perfect Filtering .................................................................................................... 57

3.5.3.4 Inverse Filtering ............................................................................................................. 57

3.5.4

Wakeup Frame Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.5.4.1 Magic Packet Detection ................................................................................................. 60

3.5.5

Receive Checksum Offload Engine (RXCOE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.5.5.1 RX Checksum Calculation ............................................................................................. 63

3.5.6

Transmit Checksum Offload Engine (TXCOE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.5.6.1 TX Checksum Calculation..............................................................................................64

3.5.7

MAC Control and Status Registers (MCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

10/100 Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.6.1

100BASE-TX Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.6.1.1 4B/5B Encoding ............................................................................................................. 65

3.6.1.2 Scrambling ..................................................................................................................... 67

3.6.1.3 NRZI and MLT3 Encoding ............................................................................................. 67

3.6.1.4 100M Transmit Driver..................................................................................................... 67

3.6.1.5 100M Phase Lock Loop (PLL) ....................................................................................... 67

3.6.2

100BASE-TX Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.6.2.1 100M Receive Input ....................................................................................................... 68

3.6.2.2 Equalizer, Baseline Wander Correction and Clock and Data Recovery ........................ 68

3.6.2.3 NRZI and MLT-3 Decoding ............................................................................................ 68

3.6.2.4 Descrambling ................................................................................................................. 69

3.6.2.5 Alignment ....................................................................................................................... 69

3.6.2.6 5B/4B Decoding ............................................................................................................. 69

3.6.2.7 Receiver Errors .............................................................................................................. 69

3.6.3

10BASE-T Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.6.3.1 10M Transmit Data Across the Internal MII Bus ............................................................ 70

3.6.3.2 Manchester Encoding .................................................................................................... 70

3.6.3.3 10M Transmit Drivers..................................................................................................... 70

3.6.4

10BASE-T Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

3.6.4.1 10M Receive Input and Squelch .................................................................................... 70

3.6.4.2 Manchester Decoding .................................................................................................... 70

3.6.4.3 Jabber Detection ............................................................................................................ 70

Revision 1.6 (07-18-11)

DATASHEET

SMSC LAN9420/LAN9420i

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

3.7

3.6.5

Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.6.6

Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.6.6.1 Re-starting Auto-negotiation .......................................................................................... 72

3.6.6.2 Disabling Auto-negotiation ............................................................................................. 72

3.6.6.3 Half vs. Full-Duplex ........................................................................................................ 72

3.6.7

HP Auto-MDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.6.8

PHY Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.6.8.1 General Power-Down..................................................................................................... 73

3.6.8.2 Energy Detect Power-Down........................................................................................... 74

3.6.9

PHY Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.6.9.1 PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST)....................................................... 74

3.6.9.2 PHY Soft Reset via PHY Basic Control Register bit 15 (PHY Reg. 0.15) ...................... 74

3.6.10 Required Ethernet Magnetics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.6.11 PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.7.1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.7.2

Related External Signals and Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

3.7.3

Device Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

3.7.4

Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.7.4.1 G3 State (Mechanical Off) ............................................................................................. 76

3.7.4.1.1 Power Management Events in

G3 ................................................................................................. 76

3.7.4.1.2 Exiting the G3 State ..................................................................................................76

3.7.4.2 D0UNINTIALIZED State (D0U) ...................................................................................... 77

3.7.4.2.1 Exiting the D0U State................................................................................................ 77

3.7.4.3 D0ACTIVE State (D0A).................................................................................................. 77

3.7.4.3.1 Power Management Events in

D0A............................................................................................... 77

3.7.4.3.2 Exiting the D0A State................................................................................................ 78

3.7.4.4 The D3HOT State .......................................................................................................... 78

3.7.4.4.1 Power Management Events in

D3HOT.......................................................................................... 78

3.7.4.4.2 Exiting the D3HOT State........................................................................................... 78

3.7.4.5 The D3COLD State ........................................................................................................79

3.7.4.5.1 Power Management Events in

D3COLD ....................................................................................... 79

3.7.4.5.2 Exiting the D3COLD State ........................................................................................ 79

3.7.5

Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.7.5.1 PHY Resets ................................................................................................................... 80

3.7.6

Detecting Power Management Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

3.7.6.1 Enabling Wakeup Frame Wake Events ......................................................................... 82

3.7.7

Enabling Link Status Change (Energy Detect) Wake Events . . . . . . . . . . . . . . . . . . . . . 82

Chapter 4 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

4.1

4.2

Register Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

System Control and Status Registers (SCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.2.1

ID and Revision (ID_REV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

4.2.2

Interrupt Control Register (INT_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

4.2.3

Interrupt Status Register (INT_STS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.2.4

Interrupt Configuration Register (INT_CFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

4.2.5

General Purpose Input/Output Configuration Register (GPIO_CFG) . . . . . . . . . . . . . . . 93

4.2.6

General Purpose Timer Configuration Register (GPT_CFG) . . . . . . . . . . . . . . . . . . . . . 95

4.2.7

General Purpose Timer Current Count Register (GPT_CNT) . . . . . . . . . . . . . . . . . . . . . 96

4.2.8

Bus Master Bridge Configuration Register (BUS_CFG) . . . . . . . . . . . . . . . . . . . . . . . . . 97

4.2.9

Power Management Control Register (PMT_CTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

4.2.10 Free Run Counter (FREE_RUN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4.2.11 EEPROM Command Register (E2P_CMD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

4.2.12 EEPROM Data Register (E2P_DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

SMSC LAN9420/LAN9420i

DATASHEET

Revision 1.6 (07-18-11)

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