3.0 Pin Description and Configuration ................................................................................................................................................ 13
4.0 Clocking, Resets, and Power Management .................................................................................................................................. 22
5.0 System Interrupts .......................................................................................................................................................................... 34
8.0 Host Bus Interface (HBI) ............................................................................................................................................................... 76
9.0 Host MAC ...................................................................................................................................................................................... 87
10.0 Serial Management ................................................................................................................................................................... 110
11.0 IEEE 1588 Hardware Time Stamp Unit .................................................................................................................................... 126
12.0 General Purpose Timer & Free-Running Clock ........................................................................................................................ 132
Appendix A: Data sheet Revision History ......................................................................................................................................... 306
The Microchip Web Site .................................................................................................................................................................... 308
Customer Change Notification Service ............................................................................................................................................. 308
Customer Support ............................................................................................................................................................................. 308
Product Identification System ........................................................................................................................................................... 309
2008-2016 Microchip Technology Inc.
DS00002286A
-page 3
LAN9311/LAN9311i
1.0
1.1
100BT
ADC
ALR
BLW
BM
BPDU
Byte
CSMA/CD
CSR
CTR
DA
DWORD
EPC
FCS
FIFO
FSM
GPIO
HBI
HBIC
Host
IGMP
Inbound
Level-Triggered Sticky Bit
PREFACE
General Terms
100BASE-T (100Mbps Fast Ethernet, IEEE 802.3u)
Analog-to-Digital Converter
Address Logic Resolution
Baseline Wander
Buffer Manager - Part of the switch fabric
Bridge Protocol Data Unit - Messages which carry the Spanning Tree
Protocol information
8-bits
Carrier Sense Multiple Access / Collision Detect
Control and Status Registers
Counter
Destination Address
32-bits
EEPROM Controller
Frame Check Sequence - The extra checksum characters added to the end
of an Ethernet frame, used for error detection and correction.
First In First Out buffer
Finite State Machine
General Purpose I/O
Host Bus Interface. The physical bus connecting the LAN9311/LAN9311i to
the host. Also referred to as the Host Bus.
Host Bus Interface Controller. The hardware module that interfaces
theLAN9311/LAN9311i to the HBI.
External system (Includes processor, application software, etc.)
Internet Group Management Protocol
Refers to data input to the LAN9311/LAN9311i from the host
This type of status bit is set whenever the condition that it represents is
asserted. The bit remains set until the condition is no longer true, and the
status bit is cleared by writing a zero.
Least Significant Bit
Least Significant Byte
Medium Dependant Interface
Media Independent Interface with Crossover
Media Independent Interface
Media Independent Interface Management
MAC Interface Layer
Multi-Level Transmission Encoding (3-Levels). A tri-level encoding method
where a change in the logic level represents a code bit “1” and the logic
output remaining at the same level represents a code bit “0”.
Most Significant Bit
Most Significant Byte
Non Return to Zero Inverted. This encoding method inverts the signal for a
“1” and leaves the signal unchanged for a “0”
Not Applicable
No Connect
Organizationally Unique Identifier
lsb
LSB
MDI
MDIX
MII
MIIM
MIL
MLT-3
msb
MSB
NRZI
N/A
NC
OUI
DS00002286A
-page 4
2008-2016 Microchip Technology Inc.
LAN9311/LAN9311i
Outbound
PIO cycle
PISO
PLL
PTP
RESERVED
Refers to data output from the LAN9311/LAN9311i to the host
Program I/O cycle. An SRAM-like read or write cycle on the HBI.
Parallel In Serial Out
Phase Locked Loop
Precision Time Protocol
Refers to a reserved bit field or address. Unless otherwise noted, reserved
bits must always be zero for write operations. Unless otherwise noted, values
are not guaranteed when reading reserved bits. Unless otherwise noted, do
not read or write to reserved addresses.
Real-Time Clock
Source Address
Start of Frame Delimiter - The 8-bit value indicating the end of the preamble
of an Ethernet frame.
Serial In Parallel Out
Serial Management Interface
Signal Quality Error (also known as “heartbeat”)
Start of Stream Delimiter
User Datagram Protocol - A connectionless protocol run on top of IP
networks
Universally Unique IDentifier
16-bits
RTC
SA
SFD
SIPO
SMI
SQE
SSD
UDP
UUID
WORD
1.2
Buffer Types
Table 1-1
describes the pin buffer type notation used in
Section 3.0, "Pin Description and Configuration," on page 13
and throughout this document.
TABLE 1-1:
Buffer Type
IS
O8
OD8
O12
OD12
PU
BUFFER TYPES
Description
Schmitt-triggered Input
Output with 8mA sink and 8mA source
Open-drain output with 8mA sink
Output with 12mA sink and 12mA source
Open-drain output with 12mA sink
50uA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-
ups are always enabled.
Note:
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to the LAN9311/LAN9311i. When
connected to a load that must be pulled high, an external resistor must be added.
PD
50uA (typical) internal pull-down. Unless otherwise noted in the pin description, internal pull-
downs are always enabled.
Note:
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely
on internal resistors to drive signals external to the LAN9311/LAN9311i. When
connected to a load that must be pulled low, an external resistor must be added.
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