BUS-63114-150Y datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Wireless rf/communication> Telecom circuit> BUS-63114-150Y

BUS-63114-150Y: DescriptionMIL-STD-1553 Data Bus Transceiver, FP-24; CategoryWireless rf/communication Telecom circuit; File Size125KB，16 Pages; ManufacturerData Device Corporation

Download Datasheet Parametric View All

BUS-63114-150Y Overview

MIL-STD-1553 Data Bus Transceiver, FP-24

BUS-63114-150Y Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	DFP
package instruction	DFP,
Contacts	24
Reach Compliance Code	compliant
JESD-30 code	S-XDFP-F24
JESD-609 code	e0
Number of functions	1
Number of terminals	24
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	UNSPECIFIED
encapsulated code	DFP
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	4.064 mm
surface mount	YES
Telecom integrated circuit types	MIL-STD-1553 DATA BUS TRANSCEIVER
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	FLAT
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Base Number Matches	1

Preview

Download Datasheet

View All

BUS-63100 SERIES

MIL-STD-1553 DATA BUS

SINGLE AND DUAL TRANSCEIVERS

BUS-63102

BUS-63105

BUS-63125

DESCRIPTION

The BUS-63100 transceivers are

complete transmitter and receiver

pairs conforming fully to MIL-STD-

1553A and 1553B. Features available

with selected models of this high reli-

ability series include: Smiths and

Harris interface type choices,

+12 V/+15 V power supply voltage

range, variable threshold levels, and

single (24-pin DDIP or square) and

completely independent dual redun-

dant (36-pin DDIP) packaging config-

urations. All models are also available

in flat packs.

The receiver section of the BUS-

63100 series accepts phase-modula-

ted bipolar data from a MIL-STD-1553

Data Bus and produces TTL signal

data at its outputs: RX Data Out and

RX Data Out. These outputs repre-

sent positive and negative variations

of the input data signals beyond an

internally fixed or externally set

threshold level. An external STROBE

input enables or disables the receiver

outputs.

The transmitter section accepts bipo-

lar TTL signal data at its TX Data and

TX Data input lines and produces

phase modulated bipolar data at the

TX Data and TX Data outputs. The

transmitters’ output voltage level is

typically 28 Vpp to 30 Vpp. An exter-

nal input, INHIBIT, takes priority over

the transmitter inputs and disables

the transmitter when activated with a

logic “1.”

The small size and different model

capabilities available with the

BUS-63100 series simplify engineer-

ing design, making it an excellent

choice for interfacing with any

MIL-STD-1553 system.

FEATURES

•

Conforms Fully to MIL-STD-1553A

and 1553B

•

Some Models Available to Military

(DESC) Drawings

•

Model Capabilities:

Single or Dual Redundant

Packaging

-12 V/-15 V Power Supply Voltage

Range Available

Harris or Smith’s I/O Compatibility

•

Small Size:

Single – 24-Pin DDIP or Square

Dual – 36-Pin DDIP Flat Packs

•

Low Power

•

High Reliability – LSI

±V

1553

DATA

BUS

+5 V

RECEIVER STROBE

BI PHASE

TTL DATA

PHASE MODULATED

BIPOLAR DATA

RX Data In

SHORT OR

LONG STUB

COUPLING

ISOLATION

TRANSFORMER

RX Data In

RECEIVER SECTION

COMPARATOR

RX Data

LIMITER

FILTER

RX Data

DECODER

COMPARATOR

TRANSMITTER SECTION

DRIVER

TX Data Out

SHAPING

NETWORK

DRIVER

TX Data Out

SHAPING

NETWORK

TX Data In

ENCODER

TX INHIBIT

FIGURE 1. BUS-63100 BLOCK DIAGRAM

DDC Custom Monolithics utilized in this product are copyright under the Semiconductor chip Protection Act.

Recommended Resources

Duplex communication circuit composed of MCl45030

Pinout circuit diagram of INA217

DC-DC converter diagram for boosting 2 batteries to 3.3V, 5V, 12V

solid state relay circuit

Load cell ratio compensation circuit

Recording head amplifier circuit

Help! Digital Logic Circuits: ...; help003 Analog electronics

Several issues about gate drivers: Several issues about gate drivers...; QWE4562009 Discrete Device

Physical address of DDR3 on DE1-SoC board?: [align=left][color=#000000]I recently used the[/color][font=Calibri][color=#000000]DE1-SoC[/color][/font][color=#000000] board to do an experiment, and I needed to use[/color][font=Calibri][color=#000...; cncqzxj FPGA/CPLD

In-depth analysis | RF front-end technology in the 5G era: With the advent of the 5G era, network base stations and user devices (such as mobile phones) have become thinner and smaller, and their energy consumption has also become lower. In order to fit small...; alan000345 RF/Wirelessly

XILINX FPGA Chip: I originally wanted to design and make an FPGA learning board by myself, taking XC7A100T as an example. I planned to buy two samples, but found that the price was ridiculously expensive, 700 RMB. Is i...; Fred_1977 FPGA/CPLD

Problems with player OSD overlay under Windows CE: Come on, everyone, stop and come in to see the problem, express your opinions, and help solve the problem~ I am currently making a player using TCPMP. The function I want to achieve is that when the f...; 6565 Embedded System

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components