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MT47H64M8B6-5EL

Description
DDR DRAM, 64MX8, 0.6ns, CMOS, PBGA60
Categorystorage    storage   
File Size8MB,133 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Environmental Compliance  
Download Datasheet Parametric View All

MT47H64M8B6-5EL Overview

DDR DRAM, 64MX8, 0.6ns, CMOS, PBGA60

MT47H64M8B6-5EL Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
package instructionFBGA, BGA60,9X11,32
Reach Compliance Codecompliant
Maximum access time0.6 ns
Maximum clock frequency (fCLK)200 MHz
I/O typeCOMMON
interleaved burst length4,8
JESD-30 codeR-PBGA-B60
JESD-609 codee3
memory density536870912 bit
Memory IC TypeDDR DRAM
memory width8
Humidity sensitivity level1
Number of terminals60
word count67108864 words
character code64000000
organize64MX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeFBGA
Encapsulate equivalent codeBGA60,9X11,32
Package shapeRECTANGULAR
Package formGRID ARRAY, FINE PITCH
Peak Reflow Temperature (Celsius)225
power supply1.8 V
Certification statusNot Qualified
refresh cycle8192
Continuous burst length4,8
Maximum standby current0.007 A
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Terminal surfaceMATTE TIN
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
Base Number Matches1
512Mb: x4, x8, x16 DDR2 SDRAM
Features
DDR2 SDRAM
MT47H128M4 – 32 Meg x 4 x 4 banks
MT47H64M8 – 16 Meg x 8 x 4 banks
MT47H32M16 – 8 Meg x 16 x 4 banks
For the latest data sheet, refer to Micron’s Web site:
http://www.micron.com/ddr2
Features
RoHS compliant
V
DD
= +1.8V ±0.1V, V
DD
Q = +1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4-bit prefetch architecture
Duplicate output strobe (RDQS) option for x8
DLL to align DQ and DQS transitions with CK
4 internal banks for concurrent operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency – 1
t
CK
Programmable burst lengths: 4 or 8
Adjustable data-output drive strength
64ms, 8,192-cycle refresh
On-die termination (ODT)
Industrial temperature (IT) option
Supports JEDEC clock jitter specification
Options
• Configuration
128 Meg x 4 (32 Meg x 4 x 4 banks)
64 Meg x 8 (16 Meg x 8 x 4 banks)
32 Meg x 16 (8 Meg x 16 x 4 banks)
• FBGA package (lead-free)
84-ball FBGA (12mm x 12.5mm) (:B)
(10mm x 12.5mm) (:D)
60-ball FBGA (12mm x 10mm) (:B)
(10mm x 10mm) (:D)
• Timing – cycle time
5.0ns @ CL = 3 (DDR2-400)
3.75ns @ CL = 4 (DDR2-533)
3.0ns @ CL = 5 (DDR2-667)
3.0ns @ CL = 4 (DDR2-667)
2.5ns @ CL = 6 (DDR2-800)
2.5ns @ CL = 5 (DDR2-800)
• Self refresh
Standard
Low-power
• Operating temperature
Commercial (0°C
T
C
85°C)
Industrial (–40°C
T
C
95°C; –40°C
T
A
85°C)
• Revision
Marking
128M4
64M8
32M16
CC
BN
CB
B6
-5E
-37E
-3
-3E
-25
-25E
None
L
None
IT
:A/:B/:D
Table 1:
Architecture
Configuration Addressing
128 Meg x 4 64 Meg x 8 32 Meg x 16
16 Meg x 8 x
4 banks
8K
16K (A0–A13)
4 (BA0–BA1)
1K (A0–A9)
8 Meg x 16 x
4 banks
8K
8K (A0–A12)
4 (BA0–BA1)
1K (A0–A9)
Table 2:
Key Timing Parameters
t
RC
Configuration 32 Meg x 4 x 4
banks
8K
Refresh Count
16K (A0–A13)
Row Addr.
4 (BA0–BA1)
Bank Addr.
Column Addr. 2K (A0–A9, A11)
Data Rate (MHz)
t
RCD
t
RP
Speed
Grade CL = 3 CL = 4 CL = 5 CL = 6 (ns) (ns)
-5E
-37E
-3
-3E
-25
-25E
400
400
400
N/A
N/A
N/A
400
533
533
667
N/A
533
N/A
N/A
667
667
667
800
N/A
N/A
N/A
N/A
800
N/A
15
15
15
12
15
12.5
15
15
15
12
15
12.5
(ns)
55
55
55
54
55
55
Note: CL = CAS latency.
PDF: 09005aef8117c18e/Source: 09005aef8211b2e6
512MbDDR2_1.fm - Rev. K 3/06 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
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