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MT47H64M8BT-25LIT

Description
DDR DRAM, 64MX8, 0.4ns, CMOS, PBGA92
Categorystorage    storage   
File Size7MB,136 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Environmental Compliance
Download Datasheet Parametric View All

MT47H64M8BT-25LIT Overview

DDR DRAM, 64MX8, 0.4ns, CMOS, PBGA92

MT47H64M8BT-25LIT Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
package instructionFBGA, BGA92,9X21,32
Reach Compliance Codeunknown
Maximum access time0.4 ns
Maximum clock frequency (fCLK)400 MHz
I/O typeCOMMON
interleaved burst length4,8
JESD-30 codeR-PBGA-B92
memory density536870912 bit
Memory IC TypeDDR DRAM
memory width8
Number of terminals92
word count67108864 words
character code64000000
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize64MX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeFBGA
Encapsulate equivalent codeBGA92,9X21,32
Package shapeRECTANGULAR
Package formGRID ARRAY, FINE PITCH
power supply1.8 V
Certification statusNot Qualified
refresh cycle8192
Continuous burst length4,8
Maximum standby current0.005 A
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Base Number Matches1
512Mb: x4, x8, x16 DDR2 SDRAM
Features
DDR2 SDRAM
MT47H128M4 – 32 Meg x 4 x 4 banks
MT47H64M8 – 16 Meg x 8 x 4 banks
MT47H32M16 – 8 Meg x 16 x 4 banks
For the latest data sheet, refer to Micron’s Web site:
http://www.micron.com/ddr2
Features
RoHS compliant
V
DD
= +1.8V ±0.1V, V
DD
Q = +1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4-bit prefetch architecture
Duplicate output strobe (RDQS) option for x8
DLL to align DQ and DQS transitions with CK
4 internal banks for concurrent operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency - 1
t
CK
Programmable burst lengths: 4 or 8
Adjustable data-output drive strength
64ms, 8,192-cycle refresh
On-die termination (ODT)
Industrial temperature (IT) option
Supports JEDEC clock jitter specification
Table 1:
Architecture
Configuration Addressing
128 Meg x 4 64 Meg x 8 32 Meg x 16
16 Meg x 8
x 4 banks
8K
16K (A0–A13)
4 (BA0–BA1)
1K (A0–A9)
8 Meg x 16
x 4 banks
8K
8K (A0–A12)
4 (BA0–BA1)
1K (A0–A9)
Options
• Configuration
128 Meg x 4 (32 Meg x 4 x 4 banks)
64 Meg x 8 (16 Meg x 8 x 4 banks)
32 Meg x 16 (8 Meg x 16 x 4 banks)
• FBGA package (lead-free)
92-ball FBGA (11mm x 19mm) (:A)
84-ball FBGA (12mm x 12.5mm) (:B)
60-ball FBGA (12mm x 10mm) (:B)
• Timing – cycle time
5.0ns @ CL = 3 (DDR2-400)
3.75ns @ CL = 4 (DDR2-533)
3.0ns @ CL = 5 (DDR2-667)
3.0ns @ CL = 4 (DDR2-667)
2.5ns @ CL = 6 (DDR2-800)
2.5ns @ CL = 5 (DDR2-800)
• Self Refresh
Standard
Low-Power
• Operating temperature
Commercial (0°C
T
C
85°C)
Industrial (-40°C
T
C
95°C; -40°C
T
A
85°C)
• Revision
pdf: 09005aef8117c18e, source: 09005aef8117c192
512MbDDR2_1.fm - Rev. J 12/05 EN
Marking
128M4
64M8
32M16
BT
CC
CB
-5E
-37E
-3
-3E
-25
-25E
None
L
None
IT
:A/:B
1
Configuration 32 Meg x 4 x
4 banks
8K
Refresh Count
16K (A0–A13)
Row Addr.
4 (BA0–BA1)
Bank Addr.
Column Addr. 2K (A0–A9, A11)
Table 2:
Key Timing Parameters
RC
(ns)
55
55
55
54
55
55
t
Data Rate (MHz)
t
Speed
RCD
t
RP
Grade CL = 3 CL = 4 CL = 5 CL = 6 (ns) (ns)
-5E
-37E
-3
-3E
-25
-25E
400
400
400
N/A
N/A
N/A
400
533
533
667
NA
533
N/A
N/A
667
667
667
800
N/A
N/A
N/A
N/A
800
N/A
15
15
15
12
15
12.5
15
15
15
12
13
12.5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
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