GS832218/36A(B/D)-400/375/333/250/200/150
119 & 165 BGA
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 2.5 V +10%/–10% core power supply
• 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119-bump and 165-bump BGA packages
• RoHS-compliant packages available
2M x 18, 1M x 36
36Mb S/DCD Sync Burst SRAMs
400 MHz–150 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
SCD and DCD Pipelined Reads
The GS832218/36A is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Functional Description
Applications
The GS832218/36A is a
37,748,736
-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
Parameter Synopsis
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
-400
2.5
2.5
395
475
4.0
4.0
290
335
-375
2.5
2.66
390
455
4.2
4.2
275
320
-333
2.5
3.3
355
415
4.5
4.5
260
305
-250
2.5
4.0
280
335
5.5
5.5
235
270
-200
3.0
5.0
240
280
6.5
6.5
200
240
-150
3.8
6.7
205
230
7.5
7.5
190
220
Unit
ns
ns
mA
mA
ns
ns
mA
mA
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
Rev: 1.03 8/2013
1/39
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS832218/36A(B/D)-400/375/333/250/200/150
GS832218/36A 165-Bump BGA Pin Description
Symbol
A
0
, A
1
An
DQ
A
DQ
B
DQ
C
DQ
D
B
A
, B
B
, B
C
, B
D
CK
BW
GW
E
1
E
3
E
2
G
ADV
ADSC, ADSP
ZZ
FT
LBO
ZQ
TMS
TDI
TDO
TCK
MCL
SCD
V
DD
V
SS
V
DDQ
NC
Type
I
I
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
I
—
—
I
I
I
—
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
Data Input and Output pins
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D
I/Os; active low (x36 Version)
Clock Input Signal; active high
Byte Write—Writes all enabled bytes; active low
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active l0w
Address Strobe (Processor, Cache Controller); active low
Sleep mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Must Connect Low
Single Cycle Deselect/Dual Cyle Deselect Mode Control
Core power supply
I/O and Core Ground
Output driver power supply
No Connect
Rev: 1.03 8/2013
4/39
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Embedded System
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