• Available in Pb-free and non Pb-free 54-pin TSOP II
package
Low Enable (BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is written into the location specified on the
address pins (A
0
through A
19
). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O
8
through I/O
15
) is written into
the location specified on the address pins (A
0
through A
19
).
Reading from the device is accomplished by enabling the chip
by taking CE LOW while forcing the Output Enable (OE) LOW
and the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is
LOW, then data from the memory location specified by the
address pins will appear on I/O
0
to I/O
7
. If Byte High Enable
(BHE) is LOW, then data from memory will appear on I/O
8
to
I/O
15
. See the truth table at the back of this data sheet for a
complete description of Read and Write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW and WE LOW).
The CY7C1061BV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout.
Functional Description
The CY7C1061BV33 is a high-performance CMOS Static
RAM organized as 1,048,576 words by 16 bits.
Writing to the device is accomplished by enabling the chip (CE
LOW) while forcing the Write Enable (WE) input LOW. If Byte
Logic Block Diagram
Pin Configurations
[1, 2]
54-pin TSOP II (Top View)
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
1M x 16
ARRAY
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN
DECODER
BHE
WE
CE
OE
BLE
I/O
12
V
CC
I/O
13
I/O
14
V
SS
I/O
15
A
4
A
3
A
2
A
1
A
0
BHE
CE
V
CC
WE
DNU/V
CC
A
19
A
18
A
17
A
16
A
15
I/O
0
V
CC
I/O
1
I/O
2
V
SS
I/O
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
I/O
11
V
SS
I/O
10
I/O
9
V
CC
I/O
8
A
5
A
6
A
7
A
8
A
9
NC
OE
V
SS
DNU/V
SS
BLE
A
10
A
11
A
12
A
13
A
14
I/O
7
V
SS
I/O
6
I/O
5
V
CC
I/O
4
ROW DECODER
Notes:
1. DNU/V
CC
Pin (#16) has to be left floating or connected to V
CC
and DNU/V
SS
Pin (#40) has to be left floating or connected to V
SS
to ensure proper application.
2. NC – No Connect Pins are not connected to the die
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
SENSE AMPS
Cypress Semiconductor Corporation
Document #: 38-05693 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 3, 2006
CY7C1061BV33
Selection Guide
–10
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Commercial
Industrial
Commercial/Industrial
10
275
275
50
–12
12
260
260
50
mA
Unit
ns
mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[3]
–0.5V to +4.6VDC
Voltage Applied to Outputs
in High-Z State
[3]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[3]
................................ –0.5V to V
CC
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
CC
3.3V
±
0.3V
DC Electrical Characteristics
Over the Operating Range
–10
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[3]
Input Leakage Current
Output Leakage Current
V
CC
Operating
Supply Current
Automatic CE
Power-down Current
—TTL Inputs
Automatic CE
Power-down Current
—CMOS Inputs
GND < V
I
< V
CC
GND < V
OUT
< V
CC
, Output Disabled
V
CC
= Max.,
f = f
MAX
= 1/t
RC
Commercial
Industrial
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.0
–0.3
–1
–1
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
275
275
70
2.0
–0.3
–1
–1
Max.
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
260
260
70
–12
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
Commercial/
Industrial
I
SB2
50
50
mA
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz, V
CC
= 3.3V
Max.
6
8
Unit
pF
pF
Thermal Resistance
[4]
Parameter
Description
Test Conditions
54-pin TSOP-II
49.95
3.34
Unit
°C/W
°C/W
Θ
JA
Θ
JC
Thermal Resistance (Junction to Ambient) Test conditions follow standard test
methods and procedures for
Thermal Resistance (Junction to Case)
measuring thermal impedance, per
EIA/JESD51.
Notes:
3. V
IL
(min.) = –2.0V and V
IH
(max) = V
CC
+ 0.5V for pulse durations of less than 20 ns.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05693 Rev. *B
Page 2 of 9
CY7C1061BV33
AC Test Loads and Waveforms
[5]
50Ω
OUTPUT
Z
0
= 50Ω
30 pF*
V
TH
= 1.5V
* Capacitive Load consists of all com-
ponents of the test environment.
ALL INPUT PULSES
3.3V
90%
GND
Rise time > 1V/ns
10%
90%
10%
Fall time: > 1V/ns
3.3V
OUTPUT
5 pF*
INCLUDING
JIG AND
SCOPE
R2
351Ω
R1 317
Ω
(a)
(b)
(c)
AC Switching Characteristics
Over the Operating Range
[6]
–10
Parameter
Read Cycle
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
V
CC
(typical) to the first access
[7]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
[8]
CE LOW to Low-Z
[8]
CE HIGH to High-Z
[8]
CE LOW to Power-Up
[9]
CE HIGH to
Power-Down
[9]
1
5
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
0
10
5
1
6
3
5
0
12
6
1
5
3
6
3
10
5
1
6
1
10
10
3
12
6
1
12
12
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
–12
Max.
Unit
Notes:
5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
DD
(3.0V). As soon as 1ms (T
power
) after reaching the
minimum operating V
DD
, normal SRAM operation can begin including reduction in V
DD
to the data retention (V
CCDR
, 2.0V) voltage.
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and specified transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.
7. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. t
power
time has to be provided initially before a Read/Write operation is
started.
8. t
HZOE
, t
HZCE
, t
HZWE
, t
HZBE
and t
LZOE
, t
LZCE
, t
\LZWE
, t
LZBE
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
±200
mV from steady-state
voltage.
9. These parameters are guaranteed by design and are not tested.
10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Chip enables must be active and WE and byte enables must be LOW to
initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge
of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document #: 38-05693 Rev. *B
Page 3 of 9
CY7C1061BV33
AC Switching Characteristics
Over the Operating Range
[6]
(continued)
–10
Parameter
Write Cycle
[10, 11]
t
WC
t
SCE
t
AW
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
t
HA
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
[8]
WE LOW to High-Z
[8]
Byte Enable to End of Write
Address Hold from Write End
7
0
10
7
7
0
7
5.5
0
3
5
8
0
12
8
7
0
8
6
0
3
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
–12
Max.
Unit
Data Retention Waveform
DATA RETENTION MODE
V
CC
3.0V
t
CDR
CE
V
DR
> 2V
3.0V
t
R
Switching Waveforms
Read Cycle No. 1
[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
12. Device is continuously selected. OE, CE, BHE and/or BHE = V
IL
.
13. WE is HIGH for Read cycle.
Document #: 38-05693 Rev. *B
Page 4 of 9
CY7C1061BV33
Switching Waveforms
(continued)
Read Cycle No. 2 (OE Controlled)
[13, 14]
ADDRESS
t
RC
CE
t
ACE
OE
BHE, BLE
t
DOE
t
LZOE
t
DBE
t
LZBE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
HZCE
t
HZBE
DATA VALID
t
PD
50%
IICC
CC
I
SB
t
HZOE
HIGH
IMPEDANCE
DATA OUT
Write Cycle No. 1 (CE Controlled)
[15, 16]
t
WC
ADDRESS
CE
t
SA
t
SCE
t
AW
t
PWE
WE
t
BW
BHE, BLE
t
SD
DATAI/O
t
HD
t
HA
Notes:
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high-impedance if OE or BHE and/or BLE = V
IH
.
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
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