COTS PEM
SSRAM
AS5SP256K36
9.0Mb, 256K x 36, Synchronous SRAM
Pipeline Burst, Single Cycle Deselect
FEATURES
•
Synchronous Operation in relation to the input Clock
•
2 Stage Registers resulting in Pipeline operation
•
On chip address counter (base +3) for Burst operations
•
Self-Timed Write Cycles
•
On-Chip Address and Control Registers
•
Byte Write support
•
Global Write support
•
On-Chip low power mode [powerdown] via ZZ pin
•
Interleaved or Linear Burst support via Mode pin
•
Three Chip Enables for ease of depth expansion without
•
•
•
•
•
•
•
•
A
A
CE1\
CE2
BWd\
BWc\
BWb\
BWa\
CE3\
VDD
VSS
CLK
GW\
BWE\
OE\
ADSC\
ADSP\
ADV\
A
A
98
97
96
95
92
91
89
87
84
99
94
93
90
88
86
85
83
Plastic Encapsulated Microcircuit
DQPc
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
DQP
DQb
DQb
VDD
VSSQ
DQb
DQb
DQb
DQb
VSSQ
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDD
VSSQ
DQa
DQa
DQa
DQa
VSSQ
VDD
DQa
DQa
DQP
SSRAM [SPB]
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQd
Data Contention.
VSSQ
VDDQ
Two Cycle load, Single Cycle Deselect
DQd
DQd
Asynchronous Output Enable (OE\)
DQPd
Three Pin Burst Control (ADSP\, ADSC\, ADV\)
3.3V Core Power Supply
3.3V/2.5V IO Power Supply
JEDEC Standard 100 pin TQFP Package,
Available in
Industrial, Enhanced,
and
Mil-Temperature
FAST ACCESS TIMES
Operating Ranges
Parameter
Symbol 200Mhz
Cycle Time
tCYC
5.0
RoHs compliant options available
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
MODE
A
A
A
A
A1
A0
NC*
NC*
VSS
VDD
NC*
A
A
A
A
A
A
A
A
Clock Access Time
Output Enable Access Time
tCD
tOE
3.0
3.0
166Mhz
6.0
3.5
3.5
50
133Mhz
7.5
4.0
4.0
Units
ns
ns
ns
GENERAL DESCRIPTION
BLOCK DIAGRAM
OE\
ZZ
CLK
CE1\
CE2
CE3\
BWE\
BWx\
GW\
ADV\
ADSC\
ADSP\
MODE
A0-Ax
BURST CNTL.
Address
Registers
Row
Decode
Column
Decode
CONTROL
BLOCK
I/O Gating and Control
Memory Array
x36
SBP
❑
Synchronous Pipeline
Burst
❋
Two (2) cycle load
❋
One (1) cycle
de-select
❋
One (1) cycle latency
on Mode change
Output
Register
Output
Driver
The AS5SP256K36 is a 9.0Mb High Performance
Synchronous Pipeline Burst SRAM, available in multiple
temperature screening levels, fabricated using High
Performance CMOS technology and is organized as a
256K x 36. It integrates address and control registers,
a two (2) bit burst address counter supporting four (4)
double-word transfers. Writes are internally self-timed
and synchronous to the rising edge of clock.
The AS5SP256K36 includes advanced control options
including Global Write, Byte Write as well as an
Asynchronous Output enable. Burst Cycle controls
are handled by three (3) input pins, ADV\, ADSP\ and
ADSC\. Burst operation can be initiated with either the
Address Strobe Processor (ADSP\) or Address Strobe
controller (ADSC\) inputs. Subsequent burst addresses
are generated internally in the system’s burst sequence
control block and are controlled by Address Advance
(ADV\) control input.
Micross Components reserves the right to change products or specifications without notice.
DQx, DQP
Input
Register
AS5SP256K36
Rev. 2.2 10/13
1
COTS PEM
SSRAM
AS5SP256K36
PIN DESCRIPTION / ASSIGNMENT TABLE
Signal Name
Clock
Address
Address
Symbol
CLK
A0, A1
A
Type
Input
Input
Input(s)
Pin
Description
This input captures all synchronous inputs to the device as well as
synchronizes the burst control functions.
37, 36
Low order, Synchronous Address Inputs and Burst counter
address inputs
35, 34, 33, 32, 31, 100,
Synchronous Address Inputs
99, 82, 81, 44, 45, 46,
47, 48, 49, 50, 43
98, 92
Active Low True Chip Enables
97
Active High True Chip Enable
88
Active Low True Global Write enable. Write to all bits
93, 94, 95, 96
Active Low True Byte Write enables. Write to byte segments
89
87
86
85
Active Low True Byte Write Function enable
Active Low True Asynchronous Output enable
Address Strobe from Controller. When asserted LOW, Address is
captured in the address registers and A0-A1 are loaded into the Bur
When ADSP\ and ADSC are both asserted, only ADSP is recognized
Address Strobe from Processor. When asserted LOW,
Address is captured in the Address registers, A0-A1 is registered in
the burst counter. When both ADSP\ and ADSC\ or both asserted,
only ADSP\ is recognized. ADSP\ is ignored when CE1\ is HIGH
Advance input Address. When asserted LOW, address in burst
counter is incremented.
Asynchronous, non-time critical Power-down Input control. Places
the chip into an ultra low power mode, with data preserved.
Bidirectional I/O Parity lines. As inputs they reach the memory
array via data register, that is triggered on the
rising edge of clock. As an output, the line delivers the valid data
stored in the array via an output register and output driver. The data
delievered is from the previous clock period of the READ cycle.
Bidirectional I/O Parity lines. As inputs they reach the memo
array via data register, that is triggered on the
rising edge of clock. As an output, the line delivers the valid data
stored in the array via an output register and output driver. The data
delievered is from the previous clock period of the READ cycle.
Interleaved or Linear Burst mode control
Core Power Supply
Core Power Supply Ground
Isolated Input/Output Buffer Supply
Chip Enable
Chip Enable
Global Write Enable
Byte Enables
Byte Write Enable
Output Enable
Address Strobe Controller
CE1\, CE3\
CE2
GW\
BWa\, BWb\,
BWc\, BWd\
BWE\
OE\
ADSC\
Input
Input
Input
Input
Input
Input
Input
Address Strobe from Processor
ADSP\
Input
84
Address Advance
Power-Down
Data Parity Input/Outputs
ADV\
ZZ
DQPa, DQPb
DQPc, DQPd
Input
Input
Input/
Output
83
64
51, 80, 1, 30
Data Input/Outputs
DQa, DQb, DQc
Input/
DQd
Output
Burst Mode
Power Supply [Core]
Ground [Core]
Power Supply I/O
I/O Ground
No Connection(s)
MODE
VDD
VSS
VDDQ
VSSQ
NC
Input
Supply
Supply
Supply
Supply
NA
52, 53, 56, 57, 58, 59,
62, 63, 68, 69, 72, 73,
74, 75, 78, 79, 2, 3, 6,
7, 8, 9, 12, 13, 18, 19,
22, 23, 24, 25, 28, 29
31
91, 15, 41, 65
90, 17, 40, 67
4, 11, 20, 27, 54, 61,
70, 77
5, 10, 21, 26, 55, 60,
Isolated Input/Output Buffer Ground
71, 76
14, 16, 38, 39, 65
No connections to internal silicon
AS5SP256K36
Rev. 2.2 10/13
Micross Components reserves the right to change products or specifications without notice.
2
COTS PEM
SSRAM
AS5SP256K36
LOGIC BLOCK DIAGRAM
A 0, A1, A
ADDRESS
REGISTER
2
A
[1:0]
MODE
ADV
CLK
Q1
ADSC
ADSP
BW
D
DQ
D ,
DQP
D
BYTE
WRITE REGISTER
DQ
C ,
DQP
C
BYTE
WRITE REGISTER
DQ
B ,
DQP
B
BYTE
WRITE REGISTER
DQ
A ,
DQP
A
BYTE
WRITE REGISTER
BURST
COUNTER
CLR
AND
LOGIC
Q0
DQ
D
,DQP
D
BYTE
WRITE DRIVER
DQ
C ,
DQP
C
BYTE
WRITE DRIVER
DQ
B ,
DQP
B
BYTE
WRITE DRIVER
DQ
A ,
DQP
A
BYTE
WRITE DRIVER
BW
C
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
BW
B
DQs
DQP
A
DQP
B
DQP
C
DQP
D
BW
A
BWE
GW
CE
1
CE
2
CE
3
OE
ENABLE
REGISTER
PIPELINED
ENABLE
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
AS5SP256K36
Rev. 2.2 10/13
Micross Components reserves the right to change products or specifications without notice.
3
COTS PEM
SSRAM
AS5SP256K36
FUNCTIONAL DESCRIPTION
cycle. Consecutive single cycle READS are supported. Once
Micross Components AS5SP256K36 Synchronous SRAM is the READ operation has been completed and deselected by use
manufactured to support today’s High Performance platforms of the Chip Enable(s) and either ADSP\ or ADSC\, its outputs
utilizing the Industries leading Processor elements including will tri-state immediately.
those of Intel and Motorola. The AS5SP256K36 supports
Synchronous SRAM READ and WRITE operations as well as A Single ADSP\ controlled WRITE operation is initiated when
Synchronous Burst READ/WRITE operations. All inputs with both of the following conditions are satisfied at the time of
the exception of OE\, MODE and ZZ are synchronous in nature Clock (CLK) HIGH: [1] ADSP\ is asserted LOW, and [2] Chip
and sampled and registered on the rising edge of the devices Enable(s) are asserted ACTIVE. The address presented to
input clock (CLK). The type, start and the duration of Burst the address bus is registered and loaded on CLK HIGH, then
Mode operations is controlled by MODE, ADSC\, ADSP\ and presented to the core array. The WRITE controls Global Write,
ADV\ as well as the Chip Enable pins CE1\, CE2, and CE3\. and Byte Write Enable (GW\, BWE\) as well as the individual
All synchronous accesses including the Burst accesses are Byte Writes (BWa\, BWb\, BWc\, and BWd\) and ADV\ are
enabled via the use of the multiple enable pins and wait state ignored on the first machine cycle. ADSP\ triggered WRITE
insertion is supported and controlled via the use of the Advance accesses require two (2) machine cycles to complete. If Global
Write is asserted LOW on the second Clock (CLK) rise, the
control (ADV\).
data presented to the array via the Data bus will be written into
The AS5SP256K36 supports both Interleaved as well as Linear the array at the corresponding address location specified by the
Burst modes therefore making it an architectural fit for either Address bus. If GW\ is HIGH (inactive) then BWE\ and one or
the Intel or Motorola CISC processor elements available on the more of the Byte Write controls (BWa\, BWb\, BWc\ and BWd\)
controls the write operation. All WRITES that are initiated in
Market today.
this device are internally self timed.
The AS5SP256K36 supports Byte WRITE operations and enters
this functional mode with the Byte Write Enable (BWE\) and the
Byte Write Select pin(s) (BWa\, BWb\, BWc\, BWd\). Global
Writes are supported via the Global Write Enable (GW\) and
Global Write Enable will override the Byte Write inputs and
will perform a Write to all Data I/Os.
The AS5SP256K36 provides ease of producing very dense
arrays via the multiple Chip Enable input pins and Tri-state
outputs.
Single Cycle Access Operations
A Single READ operation is initiated when all of the following
conditions are satisfied at the time of Clock (CLK) HIGH: [1]
ADSP\ or ADSC\ is asserted LOW, [2] Chip Enables are all
asserted active, and [3] the WRITE signals (GW\, BWE\) are
in their FALSE state (HIGH). ADSP\ is ignored if CE1\ is
HIGH. The address presented to the Address inputs is stored
within the Address Registers and Address Counter/Advancement
Logic and then passed or presented to the array core. The
corresponding data of the addressed location is propagated to
the Output Registers and passed to the data bus on the next
rising clock via the Output Buffers. The time at which the data
is presented to the Data bus is as specified by either the Clock
to Data valid specification or the Output Enable to Data Valid
spec for the device speed grade chosen. The only exception
occurs when the device is recovering from a deselected to
select state where its outputs are tristated in the first machine
cycle and controlled by its Output Enable (OE\) on following
AS5SP256K36
Rev. 2.2 10/13
A Single ADSC\ controlled WRITE operation is initiated when
the following conditions are satisfied: [1] ADSC\ is asserted
LOW, [2] ADSP\ is de-asserted (HIGH), [3] Chip Enable(s) are
asserted (TRUE or Active), and [4] the appropriate combination
of the WRITE inputs (GW\, BWE\, BWx\) are asserted
(ACTIVE). Thus completing the WRITE to the desired Byte(s)
or the complete data-path. ADSC\ triggered WRITE accesses
require a single clock (CLK) machine cycle to complete. The
address presented to the input Address bus pins at time of clock
HIGH will be the location that the WRITE occurs. The ADV\
pin is ignored during this cycle, and the data WRITTEN to the
array will either be a BYTE WRITE or a GLOBAL WRITE
depending on the use of the WRITE control functions GW\ and
BWE\ as well as the individual BYTE CONTOLS (BWx\).
Deep Power-Down Mode (SLEEP)
The AS5SP256K36 has a Deep Power-Down mode and is
controlled by the ZZ pin. The ZZ pin is an Asynchronous
input and asserting this pin places the SSRAM in a deep power-
down mode (SLEEP). While in this mode, Data integrity is
guaranteed. For the device to be placed successfully into this
operational mode the device must be deselected and the Chip
Enables, ADSP\ and ADSC\ remain inactive for the duration
of tZZREC after the ZZ input returns LOW. Use of this deep
power-down mode conserves power and is very useful in
multiple memory page designs where the mode recovery time
can be hidden.
Micross Components reserves the right to change products or specifications without notice.
4
COTS PEM
SSRAM
AS5SP256K36
SYNCHRONOUS TRUTH TABLES
CE1\
H
L
L
L
L
L
L
L
X
H
X
H
X
H
X
H
Notes:
1. X = Don’t Care
2. WT= WRITE operation in WRITE TABLE, RD= READ operation in WRITE TABLE
CE2
X
L
X
L
X
H
H
H
X
X
X
X
X
X
X
X
CE3\
X
X
H
X
H
L
L
L
X
X
X
X
X
X
X
X
ADSP\
X
L
L
H
H
L
H
H
H
X
H
X
H
X
H
X
ADSC\
L
X
X
L
L
X
L
L
H
H
H
H
H
H
H
H
ADV\
X
X
X
X
X
X
X
X
L
L
L
L
H
H
H
H
WT / RD
X
X
X
X
X
X
WT
RD
RD
RD
WT
WT
RD
RD
WT
WT
CLK
Address Accessed
NA
NA
NA
NA
NA
External Address
External Address
External Address
Next Address
Next Address
Next Address
Next Address
Current Address
Current Address
Current Address
Current Address
Operation
Not Selected
Not Selected
Not Selected
Not Selected
Not Selected
Begin Burst, READ
Begin Burst, WRITE
Begin Burst, READ
Continue Burst, READ
Continue Burst, READ
Continue Burst, WRITE
Continue Burst, WRITE
Suspend Burst, READ
Suspend Burst, READ
Suspend Burst, WRITE
Suspend Burst, WRITE
BURST SEQUENCE TABLES
Burst Control
Pin [MODE]
First Address
State
HIGH
Case 1
A1
0
0
1
1
A0
Interleaved Burst
Case 2
A1
A0
0
0
1
0
0
1
1
1
Linear Burst
Case 2
A1
A0
0
1
1
0
Case 3
A1
1
0
1
0
1
1
0
0
A0
0
1
0
1
A1
1
1
0
0
Case 4
CAPACITANCE
A
Parameter
Input Capacitance
Input/Output Capacitance
Clock Input Capacitance
Symbol
CI
CIO
CCLK
Max.
6
8
6
Units
pF
pF
pF
Fourth Address
Burst Control
Pin [MODE]
First Address
State
LOW
Case 1
A1
0
0
1
1
A0
0
1
0
1
Case 3
A1
1
0
1
0
1
1
0
0
A0
0
1
0
1
A1
Case 4
1
0
0
1
ASYNCHRONOUS TRUTH TABLE
A
Operation
Power-Down (SLEEP)
READ
WRITE
De-Selected
Fourth Address
WRITE TABLE
GW\
H
H
H
H
H
H
L
BW\
H
L
L
L
L
L
X
BWa\
X
H
L
H
H
L
X
BWb\
X
H
H
L
H
L
X
BWc\
X
H
H
H
L
L
X
BWd\
X
H
H
H
L
L
X
Operation
READ
READ
WRITE Byte [A]
WRITE Byte [B]
WRITE Byte [C], [D]
WRITE ALL Bytes
WRITE ALL Bytes
ZZ
H
L
L
L
L
OE\
X
L
H
X
X
I/O Status
High-Z
DQ
High-Z
Din, High-Z
High-Z
AC TEST LOADS
Output
Zo=50 ohm
Diagram [A]
Vt= Termination Voltage
Rt= Termination Resistor
30 pF
Vt= 1.50v for 3.3v VDDQ
Vt= 1.25v for 2.5v VDDQ
Rt = 50 ohm
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings
Parameter
Symbol
Min.
-0.3
Voltage on VDD Pin
VDD
Voltage on VDDQ Pins
VDDQ
VDD
Voltage on Input Pins
VIN
-0.3
Voltage on I/O Pins
VIO
-0.3
Power Dissipation
PD
Storage Temperature
tSTG
-65
Operating Temperatures
/IT
-40
[Screening Levels]
/ET
-40
/XT
-55
Max.
4.6
VDD+0.3
VDDQ+0.3
1.6
150
85
105
125
Units
V
V
V
V
W
C
C
C
C
R= 317 ohm@3.3v
R= 1667 ohm@2.5v
3.3/2.5v
5 pF
R= 351 ohm@3.3v
R= 1538 ohm@2.5v
Diagram [B]
Output
*Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions greater than those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum conditions
for any duration or segment of time may affect device reliability.
AS5SP256K36
Rev. 2.2 10/13
Micross Components reserves the right to change products or specifications without notice.
5
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