SN54AHC00, SN74AHC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS227H – OCTOBER 1995 – REVISED SEPTEMBER 2002
D
D
Operating Range 2-V to 5.5-V V
CC
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SN54AHC00 . . . FK PACKAGE
(TOP VIEW)
GND
NC – No internal connection
description/ordering information
The ’AHC00 devices perform the Boolean function Y
+
A
•
B or Y
+
A
)
B in positive logic.
ORDERABLE
PART NUMBER
SN74AHC00RGYR
SN74AHC00N
SN74AHC00D
SN74AHC00DR
SN74AHC00NSR
SN74AHC00DBR
SN74AHC00PWR
SN74AHC00DGVR
SNJ54AHC00J
SNJ54AHC00W
SNJ54AHC00FK
AHC00
HA00
HA00
HA00
SNJ54AHC00J
SNJ54AHC00W
SNJ54AHC00FK
TOP-SIDE
MARKING
HA00
SN74AHC00N
AHC00
ORDERING INFORMATION
TA
PACKAGE†
QFN – RGY
PDIP – N
SOIC – D
–40 C 85 C
–40°C to 85°C
SOP – NS
SSOP – DB
TSSOP – PW
TVSOP – DGV
CDIP – J
–55°C to 125°C
CFP – W
LCCC – FK
Tape and reel
Tube
Tube
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tube
Tube
Tube
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
•
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2Y
GND
NC
3Y
3A
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
4B
4A
4Y
3B
3A
3Y
1
14
13
4B
12
4A
11
4Y
10
3B
9
3A
V
CC
1A
SN54AHC00 . . . J OR W PACKAGE
SN74AHC00 . . . D, DB, DGV, N, NS,
OR PW PACKAGE
(TOP VIEW)
SN74AHC00 . . . RGY PACKAGE
(TOP VIEW)
1B
1A
NC
V
CC
4B
1Y
NC
2A
NC
2B
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
1B
1Y
2A
2B
2Y
2
3
4
5
6
7
8
4A
NC
4Y
NC
3B
3Y
1
SN54AHC00, SN74AHC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS227H – OCTOBER 1995 – REVISED SEPTEMBER 2002
FUNCTION TABLE
(each gate)
INPUTS
A
H
L
X
B
H
X
L
OUTPUT
Y
L
H
H
logic diagram, each gate (positive logic)
A
B
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Output voltage range, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±25
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
(see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
(see Note 2): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
(see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
(see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
(see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
2
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SN54AHC00, SN74AHC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS227H – OCTOBER 1995 – REVISED SEPTEMBER 2002
recommended operating conditions (see Note 4)
SN54AHC00
MIN
VCC
VIH
Supply voltage
High-level input voltage
VCC = 2 V
VCC = 3 V
VCC = 5.5 V
VCC = 2 V
VIL
VI
VO
IOH
Low-level input voltage
Input voltage
Output voltage
High-level output current
VCC = 2 V
VCC = 3.3 V
±
0.3 V
VCC = 5 V
±
0.5 V
VCC = 2 V
IOL
Low-level output current
VCC = 3.3 V
±
0.3 V
VCC = 5 V
±
0.5 V
VCC = 3.3 V
±
0.3 V
VCC = 5 V
±
0.5 V
VCC = 3 V
VCC = 5.5 V
0
0
2
1.5
2.1
3.85
0.5
0.9
1.65
5.5
VCC
–50
–4
–8
50
4
8
100
20
0
0
MAX
5.5
SN74AHC00
MIN
2
1.5
2.1
3.85
0.5
0.9
1.65
5.5
VCC
–50
–4
–8
50
4
8
100
20
V
V
V
V
MAX
5.5
UNIT
V
m
A
mA
m
A
mA
ns/V
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2V
IOH = –50
m
A
VOH
IOH = –4 mA
IOH = –8 mA
IOL = 50
m
A
VOL
IOL = 4 mA
IOL = 8 mA
II
ICC
Ci
VI = 5.5 V or GND
VI = VCC or GND,
IO = 0
3V
4.5 V
3V
4.5 V
2V
3V
4.5 V
3V
4.5 V
0 V to 5.5 V
5.5 V
TA = 25°C
MIN
TYP
MAX
1.9
2.9
4.4
2.58
3.94
0.1
0.1
0.1
0.36
0.36
±0.1
2
2
3
4.5
SN54AHC00
MIN
1.9
2.9
4.4
2.48
3.8
0.1
0.1
0.1
0.5
0.5
±1*
20
MAX
SN74AHC00
MIN
1.9
2.9
4.4
2.48
3.8
0.1
0.1
0.1
0.44
0.44
±1
20
10
V
V
MAX
UNIT
m
A
m
A
pF
VI = VCC or GND
5V
2
10
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
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3
SN54AHC00, SN74AHC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS227H – OCTOBER 1995 – REVISED SEPTEMBER 2002
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
±
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
A or B
A or B
TO
(OUTPUT)
Y
Y
LOAD
CAPACITANCE
CL = 15 pF
CL = 50 pF
TA = 25°C
MIN
TYP
MAX
5.5*
5.5*
8
8
7.9*
7.9*
11.4
11.4
SN54AHC00
MIN
1*
1*
1
1
MAX
9.5*
9.5*
13
13
SN74AHC00
MIN
1
1
1
1
MAX
9.5
9.5
13
13
UNIT
ns
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
A or B
A or B
TO
(OUTPUT)
Y
Y
LOAD
CAPACITANCE
CL = 15 pF
CL = 50 pF
TA = 25°C
MIN
TYP
MAX
3.7*
3.7*
5.2
5.2
5.5*
5.5*
7.5
7.5
SN54AHC00
MIN
1*
1*
1
1
MAX
6.5*
6.5*
8.5
8.5
SN74AHC00
MIN
1
1
1
1
MAX
6.5
6.5
8.5
8.5
UNIT
ns
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, V
CC
= 5 V, C
L
= 50 pF, T
A
= 25°C (see Note 5)
PARAMETER
VOL(P)
VOL(V)
VOH(V)
VIH(D)
Quiet output, maximum dynamic VOL
Quiet output, minimum dynamic VOL
Quiet output, minimum dynamic VOH
High-level dynamic input voltage
3.5
1.5
SN74AHC00
MIN
TYP
0.3
–0.3
4.6
MAX
0.8
–0.8
UNIT
V
V
V
V
V
VIL(D)
Low-level dynamic input voltage
NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
No load,
f = 1 MHz
TYP
9.5
UNIT
pF
4
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SN54AHC00, SN74AHC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS227H – OCTOBER 1995 – REVISED SEPTEMBER 2002
PARAMETER MEASUREMENT INFORMATION
RL = 1 kΩ
S1
VCC
Open
GND
From Output
Under Test
CL
(see Note A)
Test
Point
From Output
Under Test
CL
(see Note A)
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
S1
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
VCC
Timing Input
tw
VCC
tsu
Data Input
0V
50% VCC
50% VCC
th
0V
VCC
50% VCC
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC
50% VCC
tPZL
50% VCC
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
50% VCC
50% VCC
0V
tPLZ
≈V
CC
VOL + 0.3 V
tPHZ
VOH – 0.3 V
VOH
≈0
V
VOL
Input
50% VCC
50% VCC
VOLTAGE WAVEFORMS
PULSE DURATION
Input
tPLH
In-Phase
Output
tPHL
Out-of-Phase
Output
50% VCC
50% VCC
0V
tPHL
Output
Control
50% VCC
VOH
50% VCC
VOL
tPLH
Output
Waveform 1
S1 at VCC
(see Note B)
50% VCC
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr
≤
3 ns, tf
≤
3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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